Role Summary
This position is focused on the design and layout of CMOS and metallization test structures. The role involves collaboration with various teams to develop and optimize semiconductor test structures.
Experience Level
Entry-level. Requires a Master's degree in a relevant field.
Responsibilities
The responsibilities include:
- Supporting process development activities for memory cell-based test structures.
- Building completed Test Element Groups (TEGs) with high confidence functionality on Silicon.
- Implementing solutions to study failure mechanisms and monitor silicon health.
- Assisting with parametric correlation and debugging for design accuracy.
- Verifying and validating test structure documentation and related parametric information.
Requirements
The minimum qualifications for this role are:
- Master’s degree in Electrical, Computer, or Microelectronic Engineering.
- Hands-on experience with EDA tools such as Cadence Virtuoso and Calibre.
- Strong circuit design, layout, schematic, and verification skills.
- Knowledge of semiconductor device physics, operation, parametric testing, and DFM.
- Ability to interpret DUT definitions and deliver completed TEGs.
- Excellent problem-solving and interpersonal skills.
- Willingness to learn and explore new skills.
- Ability to drive decisions through data and metrics.
Education Requirements
A Master’s degree in Electrical, Computer, or Microelectronic Engineering is required.
About the Company
Company: Micron Technology
Headquarters: Boise, Idaho, USA
Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.

Date Posted: 2026-04-08