MTS SoC DFT Engineer, HBM

Job Title

MTS SoC DFT Engineer, HBM

Role Summary

Owner of design-for-test (DFT) solutions for high-bandwidth memory (HBM) system-on-chip (SoC) base‑die designs, working within the Heterogeneous Integration Group (HIG) to enable manufacturability, quality, and silicon bring‑up across HBM generations.

The role partners with RTL, physical design, verification, CAD/methodology, product engineering, test, and manufacturing teams to define, implement, and sign off SoC-level DFT architecture and flows.

Experience Level

Senior - typically requires 10+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs/SoCs.

Responsibilities

Primary duties include architecture, implementation, integration, and sign-off of DFT at block to full-chip scale for HBM base‑die SoCs.

• Own SoC-level DFT structures and implementation: scan, MBIST, LBIST (where applicable), boundary scan (JTAG), and test access architectures.
• Define and drive DFT architecture early in the design cycle to align with integration, floorplanning, timing, power, and physical requirements.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels in partnership with RTL design and SoC integration teams.
• Complete and sign off DFT flows, including linting, CDC checks, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design to optimize DFT for placement, routing, timing closure, and DRC/LVS signoff.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth pre- and post-silicon bring-up.
• Partner with CAD and methodology teams to standardize and improve DFT flows, participate in technical reviews, and mentor engineers.
• Apply Gen-AI and agentic-AI techniques to improve DFT workflows and methodologies.

Requirements

Must-have technical skills and relevant experience; preferred items listed separately.

• Must-have: Hands-on experience with SoC DFT architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience across full RTL-to-GDS flows and collaboration with synthesis, static timing analysis (STA), and physical design teams.
• Proficiency with industry-standard EDA tools (Siemens, Synopsys, and/or Cadence) for DFT and implementation.
• Proven track record of DFT flow sign-off: linting, CDC checks, DFT rule checks, ATPG readiness, and coverage closure.
• Nice-to-have: Experience with large, complex SoCs integrating multiple IP blocks; strong RTL debugging and design-analysis skills.
• Familiarity with scripting for flow automation (Python, Tcl, Perl).
• Familiarity with memory systems (DRAM, HBM) and related JEDEC specifications.
• Experience applying Gen-AI/automation to DFT or verification workflows.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. (Minimum qualifications specify a Bachelor's in EE/CE or related field, or equivalent practical experience.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.