MTS Silicon System Architect

Job Title

MTS Silicon System Architect

Role Summary

Senior technical role responsible for defining IP architecture and micro-architecture for complex digital IP blocks within ASIC/SoC products. The role partners with design, verification, validation, software, and system teams to deliver reusable, production-quality IP and support SoC integration and post-silicon debug.

Experience Level

Senior — requires extensive hands-on experience; posting specifies 15+ years in ASIC/SoC design with significant IP architecture or technical leadership experience.

Responsibilities

The role owns IP architecture through release, drives design quality, and ensures clean system integration.

• Define and own IP architecture and micro-architecture for complex digital IP blocks.
• Translate system and customer requirements into scalable architectural solutions and maintain architecture specifications.
• Provide technical leadership from architecture definition through IP release; drive architectural reviews focused on performance, area, power, and scalability trade-offs.
• Partner with design and verification teams to review micro-architecture and RTL, validate test plans and coverage strategies, and debug functional and integration issues.
• Support SoC integration, bring-up, and post-silicon debug as needed.
• Architect IP involving SoC interfaces and datapaths (DMA/data-movement engines, interconnects, control interfaces, networking and security datapaths) and ensure integration with system fabrics.
• Collaborate across planning, software, validation, and system teams; contribute to IP roadmaps and mentor engineers.

Requirements

Must-have technical experience and skills. Preferred items are listed separately.

• 15+ years' proven ASIC/SoC design experience with significant focus on IP architecture or technical leadership; experience owning IP from concept through tape-out or production release.
• Proven experience in senior technical or lead design roles.
• Expertise in IP architecture and micro-architecture definition and RTL design.
• Practical knowledge of ASIC design flows, power-on, integration, and post-silicon debug.
• Experience with standard SoC interfaces (interconnects, control buses, high-speed interfaces) and data-movement engines.
• Familiarity with RTL review and verification tool flows: lint, CDC, synthesis, timing closure.
• Proficiency in hardware description languages (e.g., SystemVerilog) and scripting for automation and debug.

Education Requirements

Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

Nice-to-have experience that strengthens a candidate's fit.

• Experience developing reusable IP across multiple products or platforms.
• Background in high-throughput or data-handling IPs; exposure to networking, security, or system infrastructure IPs.
• Experience working with geographically distributed teams.

Key Competencies

• Strong architectural judgment and system-level thinking; ability to balance design trade-offs pragmatically.
• Clear, structured technical communication and high ownership perspective with focus on quality and reuse.
• Comfort operating across architecture, design, and integration boundaries; effective use of approved AI tools where applicable.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.