MTS - HIG HBM Architecture Engineer

Job Title

MTS - HIG HBM Architecture Engineer

Role Summary

Join the High-Performance Integrated Group (HIG) in Technology and Products Group to define and own IO design quality for High Bandwidth Memory (HBM) products. Build and maintain end-to-end design quality systems, drive silicon-to-simulation correlation, and create cross-team data collection frameworks so silicon learnings are fed back into the next-generation design.

Experience Level

Senior level - requires 10+ years of relevant engineering or design engineering experience focused on high-speed IO, PLL, Tx/Rx, equalization, or clock-tree design.

Responsibilities

Deliver and operate processes and systems that improve IO design quality from architecture through silicon.

• Define and standardize IO design quality processes for HBM products.
• Lead high-speed IO design architecture activities for HBM.
• Correlate silicon measurements and simulation results with Product Engineering for circuit-level analysis.
• Collect, analyze, and maintain cross-team silicon data; build frameworks for systematic feedback into designs.
• Solicit and coordinate input from Standards, CAD, modeling, and verification teams.
• Use AI-assisted analytics to accelerate root-cause identification from complex silicon datasets.
• Drive cross-group communication and contribute to standardization and future memory-generation innovation.

Requirements

Must-have technical skills and experience for successful execution of the role.

• Industrial experience with high-speed clocking and IO at 32 Gbps or higher.
• Strong IO circuit design background covering analog and digital design and simulation.
• Experience with circuit verification, layout verification, and parasitic extraction.
• Familiarity with one or more off-chip protocols (examples: UCIe, HBM, DDR, PCIe, MIPI).
• Practical understanding of modern device characteristics and hands-on design experience.
• Proven problem-solving, technical documentation, and clear verbal/written communication skills.
• Experience in simulation-to-silicon correlation, methodology development, and data-driven decision making; willingness to apply AI analytics.
• Preferred: prior circuit debug experience via Product Engineering and knowledge of advanced packaging (CoWoS, HBM stack, D2D).

Education Requirements

MS or PhD in Electrical Engineering (EE) is required. The posting also specifies 10+ years of relevant engineering or design engineering experience in high-speed IO, PLL, Tx/Rx, equalization, or clock-tree design.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.