MTS - DPG Layout

Job Title

MTS - DPG Layout

Role Summary

Senior layout engineer in Micron's DRAM Engineering Group responsible for full-chip and block-level analog/custom layout delivery for advanced CMOS processes. The role leads technical decisions, defines layout standards, and collaborates with design, verification, CAD, DTCO, PI and cross‑functional teams across Micron's global sites.

Experience Level

Senior-level. Target candidate has 15+ years of experience in analog/custom layout design and leadership of multiple projects and tape-outs.

Responsibilities

Primary duties to ensure timely, high-quality layout delivery and to grow layout capability.

• Design and develop full-chip and block-level layouts; make technical decisions spanning analog, digital, memory, ESD, and full‑chip EM/IR.
• Define and drive layout guidelines, standards, and best practices for quality and manufacturability.
• Perform physical verification tasks (DRC/LVS/Antenna) and document quality checks.
• Plan, estimate area/time, schedule, delegate, and execute multiple projects to meet tape‑out milestones.
• Collaborate with cross-functional teams (Design, Verification, CAD, DTCO, PI) to define and execute layout solutions.
• Develop automation, scripts, and productivity improvements for layout flows.
• Mentor and review work of junior layout engineers; build and manage high-performing teams.
• Communicate effectively with global engineering teams (US, Japan, Germany) to coordinate deliverables.
• Drive innovation in layout methodologies and contribute to technical disclosures, papers, or seminars.
• Compose clear technical prompts for AI-assisted design/verification tasks and validate AI outputs before use.

Requirements

Must-have technical skills and experience for immediate contribution.

• 15+ years experience in analog/custom layout design for advanced CMOS processes.
• Expertise with Cadence VLE/VXL and Mentor/Calibre DRC & LVS flows.
• Hands-on experience with critical analog blocks (e.g., temperature sensors, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pumps, current mirrors, comparators, differential amplifiers).
• Experience with memory layouts including DRAM, SRAM, CAM, OTP.
• Strong understanding of analog layout fundamentals: matching, electromigration, latch-up, coupling/crosstalk, IR drop, parasitics and their impact on speed, capacitance, power and area.
• Proven track record of leading multiple projects to tape-out and delivering full‑chip layouts on schedule.
• Experience in scripting and layout automation to improve productivity.
• Strong problem-solving skills in physical layout verification and excellent verbal and written communication.
• Ability to hire, mentor, and manage layout engineers to meet global standards.

Nice-to-have: publication record or seminar/disclosure experience; experience in layout team leadership at scale; demonstrated prior work using AI tools for design/verification with validated workflows.

Education Requirements

BE or MTech in Electronics / VLSI Engineering (or equivalent technical degree) as stated in the posting.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.