MTS ASIC Architect

Job Title

MTS ASIC Architect

Role Summary

Provide architectural leadership for ASIC and logic-based DRAM solutions within the DRAM ASIC Architecture team. The role spans near-term product execution and long-term technology direction, working across design, product, systems, and ecosystem partners to deliver scalable, high-bandwidth, energy-efficient, and reliable memory solutions.

Accountable for architecture decisions that affect bandwidth density, latency, power, RAS, and system observability; mentors execution teams and collaborates with cross-functional stakeholders to ensure first-silicon success.

Experience Level

Senior — approximately 15 years of relevant industry experience.

Responsibilities

Key responsibilities include leading architecture decisions, performing technical reviews, and mentoring teams to achieve product and technology goals.

• Lead architectural trade-off analysis across DRAM silicon, ASIC logic, packaging, and system integration considering power delivery, thermals, signal integrity, and form-factor constraints.
• Define functional partitioning and interfaces between DRAM devices and logic die to optimize performance, power, and scalability.
• Drive architectural analysis including PPA evaluation, IO timing considerations, and scalability planning for next-generation DRAM products.
• Perform micro-architectural, RTL, and design reviews, and lead verification and coverage reviews to ensure high-quality execution and first-silicon success.
• Influence cross-functional decisions with data-driven analysis and clear technical reasoning.
• Serve as a technical mentor and architectural authority for execution teams; guide mitigation strategies in collaboration with design and validation teams.

Requirements

Concise summary of must-have technical skills and demonstrated behaviors. Degree information is summarized in the Education Requirements section below.

Must-have:

• Extensive experience in micro-architecture and architectural definition of SoCs or subsystems; proven track record leading technical definition across peers and design teams.
• High-speed digital logic design experience and practical knowledge of RTL and verification processes.
• Deep understanding of DRAM architecture trade-offs affecting bandwidth, latency, power efficiency, and reliability (RAS).
• Experience performing architecture, RTL, and verification reviews and guiding mitigation strategies.
• Demonstrated technical leadership, mentoring experience, and ability to work independently and in ambiguous environments.

Nice-to-have / Preferred:

• Experience with multi-die interfaces and integration across DRAM silicon, ASIC logic, packaging, and high-speed interfaces.
• Experience engaging with customers, ecosystem partners, or standards organizations (e.g., JEDEC).
• Demonstrated leadership across multiple projects or product generations and familiarity with system-level trade-offs (performance, power, SI, thermals, cost).

Education Requirements

Bachelor's degree or higher in Electrical Engineering, Computer Engineering, Computer Science, or a related field is expected. A Master’s or PhD in a relevant engineering or computer science field is preferred; equivalent practical experience is acceptable.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.