MTS - Analog Layout

Job Title

MTS - Analog Layout

Role Summary

Lead full‑custom analog/mixed‑signal layout for complex IP blocks and own layout quality from floor‑planning through tape‑out. Collaborate with circuit designers, foundry contacts, and CAD teams to meet performance, reliability, and signoff requirements across advanced and planar process nodes.

Experience Level

Mid-level individual contributor with technical leadership and mentorship responsibilities. Specific years of experience not specified.

Responsibilities

Primary responsibilities include complete layout delivery, verification, mentorship, and methodology development.

• Perform full‑custom layout for analog and mixed‑signal blocks: bandgaps, LDOs/regulators, charge pumps, PLLs, delay lines, oscillators, IO/PHY analog, temperature sensors, bias circuits, and ESD devices.
• Ensure device matching, symmetry, noise isolation, substrate strategies, and robust power/ground planning to meet yield and reliability goals.
• Drive layout verification and signoff activities: DRC, LVS, ERC, ANTENNA, EM/IR, ESD, and other reliability checks; manage waivers and convergence with foundry and CAD teams.
• Translate circuit performance targets into layout strategies in noise‑sensitive mixed‑signal environments and work closely with circuit designers.
• Provide technical guidance and conduct design reviews for junior and mid‑level layout engineers; develop and document best‑known methods, templates, and IP reuse strategies.
• Own floor‑planning through tape‑out readiness, including DFM and yield considerations.

Requirements

Must-have skills and experience:

• Proven experience in analog/mixed‑signal full‑custom layout and signoff workflows.
• Strong expertise in advanced FinFET nodes (for example TSMC 3nm, 5nm): fin quantization, multi‑Vt/multi‑fin strategies, and advanced metal stack planning.
• Experience with planar CMOS nodes (e.g., 40nm, 65nm, 90nm), foundry PDKs, layout‑dependent effects, and process variability.
• Experience driving DRC/LVS/ERC/ANTENNA/EM‑IR/ESD checks and working with foundry/CAD teams for waivers and signoff.
• Proficiency in Python/scripting and EDA automation; ability to develop and integrate AI/ML or generative AI approaches for layout and verification.
• Ability to mentor engineers and document methodology improvements.

Nice-to-have:

• Experience across both advanced FinFET and legacy planar processes in production tape‑outs.
• Prior layout work on PLLs, charge pumps, IO/PHY analog, and regulator IP.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.