ML Hardware Verification Manager

Job Title

ML Hardware Verification Manager

Role Summary

Lead and manage a team responsible for design verification of custom ML accelerators and silicon platforms. Ensure functional correctness, coverage closure, and silicon readiness through verification strategies across compute engines, memory hierarchies, and interconnects.

Partner with ML researchers, architects, RTL designers, software, and post-silicon teams to drive tape-out milestones and verification automation.

Experience Level

Senior - requires 12+ years in hardware design verification and 5+ years managing hardware engineering teams.

Responsibilities

Principal responsibilities include planning verification strategy, delivering tape-out ready verification, and scaling team and infrastructure.

• Lead and mentor a hardware verification engineering team; set technical direction and deliver against tape-out schedules.
• Define and own verification strategy for ML hardware blocks: compute engines, memory hierarchies, and on-chip interconnects.
• Develop and maintain UVM testbenches, constrained-random stimulus, assertions, and formal verification flows.
• Drive functional coverage closure, regression management, and sign-off criteria for multiple silicon projects.
• Collaborate with RTL, physical design, post-silicon validation, and software teams to reduce verification risk and support bring-up.
• Establish verification infrastructure and automation to improve reuse and shorten cycles.
• Communicate verification status, risks, and mitigation plans to leadership and stakeholders.

Requirements

Must-have technical skills and demonstrated experience.

• Extensive experience with functional simulation, coverage-driven verification, and formal verification of digital logic.
• Strong knowledge of SystemVerilog, SystemVerilog Assertions (SVA), X-propagation analysis, UPF power-aware flows, and gate-level simulations.
• Proven experience with UVM-based testbench architecture and constrained-random verification on complex SoC or accelerator designs.
• Track record of driving verification closure for tape-out: coverage analysis, regression management, and sign-off.
• Experience collaborating across RTL design, physical design, emulation/post-silicon validation, and software teams throughout the silicon lifecycle.
• Experience with ML IPs and silicon development (e.g., accelerators, memory subsystems, interconnects).

Nice-to-have:

• Familiarity with emulation, FPGA prototyping, or hybrid pre-silicon validation platforms.
• Experience in SW/HW co-design, firmware interaction testing, and developing software unit tests or kernels.
• Past work on ML accelerator components such as matrix multiply units, dataflow engines, or HBM interfaces.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Science, or a relevant field. Preferred: Master's or PhD in Electrical Engineering, Computer Science, or a related field.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.