Mixed Signal Systems and Verification Engineer II

Job Title

Mixed Signal Systems and Verification Engineer II

Role Summary

The Mixed-Signal Systems and Verification Engineer II will develop and verify analog and mixed-signal behavioral models and integrate them with RTL verification environments. The role works on verification of AMS IP (e.g., ADC/DAC, PLL, SerDes) and requires collaboration across analog, digital, and systems teams to deliver silicon-quality verification.

Experience Level

Mid-level. Typical experience indicated is 0–2+ years in digital, analog, or mixed-signal design and verification environments.

Responsibilities

Primary responsibilities focus on developing behavioral models, verifying mixed-signal functionality, and maintaining verification infrastructure.

• Develop simulation-efficient analog and mixed-signal behavioral models (real-number models) in SystemVerilog.
• Verify that behavioral models accurately represent analog schematics and design intent.
• Integrate analog behavioral models with RTL test environments and SystemVerilog testbenches.
• Create and run test scenarios and assertions (including analog assertion‑based verification) to validate functionality against specifications.
• Support verification of AMS blocks such as filters, ADC/DAC, VCO, A/DPLL, SerDes, LNA, mixers, and related IP.
• Debug verification failures across analog, digital, and mixed-signal domains.
• Develop and maintain verification infrastructure: testbenches, environments, automation scripts, and documentation of assumptions and methodology.
• Collaborate cross-functionally with design, systems, and IP teams to ensure verification coverage and address constraints.

Requirements

Must-have technical skills and experience are listed first; preferred skills are noted separately.

• Strong understanding of SystemVerilog and mixed-signal verification concepts.
• Experience or coursework with real-number modeling (RNM) constructs such as wreal, UDN/UDT/UDR, and Verilog-AMS.
• Basic understanding of analog and mixed-signal blocks (ADCs, DACs, PLLs, SerDes, RF or signal-processing components).
• Familiarity with Cadence Virtuoso Schematic Composer and ADE.
• Experience developing and maintaining verification infrastructure, including testbenches, environments, and automation scripts.
• Ability to debug cross-domain issues and communicate results clearly in writing and verbally.

Nice-to-have:

• Scripting experience for verification and automation (Python or Perl).
• Exposure to SystemVerilog UVM methodologies and FPGA prototyping.
• Experience with low-power architectures, hardware acceleration platforms (Palladium, Protium), and industry interfaces (PCIe, USB, DDR).
• Familiarity with revision control systems (e.g., SOS, SVN, GIT).

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is required; MSEE or PhD is preferred.

Apply

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.