Senior Design Verification Engineer
Senior Verification Engineer in the Switch IP group responsible for functional verification of complex networking ASIC blocks. The role focuses on developing and maintaining UVM/SystemVerilog verification environments and collaborating with architecture, design, firmware, and post-silicon teams.
The team delivers networking silicon for data center and AI infrastructure; this position contributes across the development cycle from reference models to post-silicon validation.
Senior — 7+ years of hands-on ASIC/RTL verification experience.
Primary responsibilities include:
Must-have technical skills and experience:
B.Sc. or M.Sc. in Electrical or Computer Engineering (or closely related technical field). Equivalent practical experience may be considered.
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
