Mixed Signal Logic Design Engineer

Job Title

Mixed Signal Logic Design Engineer

Role Summary

The Mixed Signal Logic Design Engineer will develop RTL and logic for mixed-signal subsystems and high-speed IP, ensuring power, performance, area, and timing targets are met for integration into complex SoCs.

The role collaborates with SoC architects, analog teams, and verification groups to define interfaces, manage synchronization between analog and digital domains, and support integration and customer enablement.

Experience Level

Senior — requires substantial experience; posting specifies 10+ years of relevant industry experience.

Responsibilities

Key responsibilities include design, verification collaboration, integration support, and timing/power optimization.

• Develop logic design and RTL (Verilog/SystemVerilog) for mixed-signal subsystems and high-speed IP blocks.
• Define interfaces and synchronize analog and digital domains in collaboration with SoC architects and analog teams; manage CDC requirements.
• Apply and optimize low-power techniques such as UPF coding, power gating, and clock gating to meet PPA goals.
• Perform static timing analysis (STA), manage timing exceptions, and resolve timing closure issues.
• Review verification plans, debug RTL tests, and collaborate with verification teams to ensure feature coverage.
• Prepare technical documentation and support SoC customers for high-quality IP integration.

Requirements

Must-have technical skills and relevant experience.

Must-have:

• 10+ years of experience in digital and mixed-signal logic design.
• Proficiency in RTL coding with Verilog/SystemVerilog and strong digital design fundamentals.
• Hands-on experience with low-power design techniques (UPF, clock gating, power gating) and related debug.
• Deep knowledge of static timing analysis (STA) and clock domain crossing (CDC) strategies.
• Experience with EDA flows and tools, including lint tools and timing exception management.
• Experience with memory and interface protocols such as DDR/LPDDR and UCIe on advanced technology nodes.
• Strong debugging, technical writing, and cross-functional collaboration skills.

Nice-to-have:

• Experience with mixed-signal simulation methodologies and formal verification tools.
• Post-silicon debug experience and familiarity with high-bandwidth memories (HBM).
• Leadership, mentoring, or task-force management experience.

Education Requirements

Master's degree in Electrical Engineering (or equivalent) is specified; equivalent practical experience is acceptable. The posting also indicates 10+ years of related industry experience.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.