Mid-level Physical Design Engineer, CPU

Job Title

Mid-level Physical Design Engineer, CPU

Role Summary

Work on block-level physical implementation of CPU core blocks within the RTL-to-GDS flow, supporting synthesis, floorplanning, place-and-route, timing/power closure, and physical verification. Collaborate with RTL, verification, clocking, and full-chip teams to meet timing, power, and area (PPA) targets on advanced process nodes.

This role provides growth in physical design and SoC development for high-performance, power-efficient CPU designs.

Experience Level

Mid-level — typically requires a Bachelor's degree plus 5+ years of relevant experience, or a Master's degree plus 3+ years of relevant experience.

Responsibilities

Typical responsibilities include:

• Execute physical design implementation for CPU core blocks or subsystems.
• Perform synthesis, floorplanning, place and route (PnR), and design-closure activities.
• Conduct static timing analysis (STA), power analysis, and physical verification.
• Identify and debug timing, power, and design-rule violations.
• Contribute to achieving timing, power, and area (PPA) targets.
• Develop and maintain design automation scripts (TCL and other scripting languages).
• Collaborate with RTL design, verification, clocking, and full-chip teams.
• Support improvements to design flows, methodologies, and best practices.
• Document technical work and share knowledge within the team.

Requirements

Must-have:

• Experience with integrated circuit design tools (Synopsys or Cadence) including logic synthesis, place-and-route, STA, and design closure.
• Experience with PV convergence, including static timing and power analysis.
• Experience in chip physical-design verification: formal equivalence, timing checks, electrical rules, DRC/LVS, noise and electromigration checks.
• Scripting skills: TCL required plus at least one other interpreted language (Perl, Python, Ruby).
• Experience synthesizing a digital logic block integrated into a large SoC or IP.
• Strong analytical/problem-solving skills and effective cross-functional communication.

Nice-to-have:

• Exposure to CPU micro-architecture.
• Physical-design best practices for floor-planning, routing techniques, and clock distribution.
• Advanced STA, noise analysis, and reliability verification techniques.
• RTL-to-GDS methodologies and formal equivalence flows.
• Familiarity with Synopsys Fusion Compiler / ICC2 / PrimeTime or Cadence Genus / Innovus tool suites.

Education Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field with 5+ years of relevant work experience; or a Master's degree in the same fields with 3+ years of relevant work experience. No specific certifications were listed.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.