Memory System Designer and Place and Route Engineer
BroadcomJob Title
Memory System Designer and Place and Route Engineer
Role Summary
Join the Central Engineering Group to architect, implement, and physically realize large memory blocks and subsystem designs. The role covers subsystem architecture, Verilog RTL implementation, place-and-route, and driving design closure for memory subsystems.
Location: Mendota Heights, MN. Annual base salary range: $108,000 - $172,800.
Experience Level
Senior — typically requires a minimum of 8 years of relevant experience.
Responsibilities
Primary responsibilities include:
- Architect and design memory subsystems
- Implement RTL for subsystem designs (Verilog)
- Perform place-and-route and other physical design tasks
- Drive design closure: timing, DRC, LVS, EM/IR, etc.
- Gate-level netlist synthesis and support logical equivalency checking
Requirements
Must-have technical skills and experience:
- Strong digital design skills
- Proficient in writing and debugging Verilog RTL
- Place-and-route expertise and experience with STA, DRC, EM/IR tools
- Experience with synthesis tools and running gate-level synthesis
- Ability to run and debug logical equivalency checkers
- Proficient in scripting and automation (Python)
- Familiarity with memory behavior and large memory block design
- Good communication, interpersonal, and leadership skills; self-driven and able to multitask
Nice-to-have: experience building automation frameworks or leading memory subsystem projects.
Education Requirements
Bachelor's degree in Electrical Engineering is stated as a requirement.
About the Company
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
