Memory Silicon Validation Engineer

Job Title

Memory Silicon Validation Engineer

Role Summary

Join the Silicon Co-Design Group to lead high-speed memory bring-up, characterization, and qualification for NVIDIA GPU, CPU, and SoC programs. The role focuses on root-causing memory marginality across DRAM, controller, PHY, board, and workload, and building repeatable, AI-assisted qualification workflows.

Experience Level

Senior - requires demonstrated senior-level experience. The posting requests 4+ years in the semiconductor industry with at least 3 years directly on memory interface bring-up, characterization, and qualification on shipped silicon.

Responsibilities

Work across engineering teams to bring up and qualify high-speed memory interfaces and convert findings into productized fixes and repeatable methodology.

• Bring up GDDR, LPDDR, and HBM interfaces from first power-on through full PVT characterization and productization.
• Own functional validation, IO tuning, timing margin analysis, and multi-vendor DRAM qualification across controller, PHY, and DRAM devices.
• Lead cross-team root-cause investigations and close ambiguous memory failures with reproducible workarounds and fixes.
• Design and deploy AI-enabled workflows for shmoo/margin analysis, failure-signature detection, and workload-vs-margin correlation.
• Partner with pre-silicon architecture, design, and DV teams to align post-silicon validation plans and feed learnings back into methodology.
• Collaborate with global teams including PCB, firmware, software, DRAM vendors, and manufacturing partners.

Requirements

Core technical and practical skills required to perform the role.

• 4+ years in the semiconductor industry, with at least 3 years on memory interface bring-up, characterization, and qualification on shipped silicon.
• Deep protocol and physical-layer knowledge of GDDR, LPDDR, or HBM: training, calibration, IO tuning, timing margin, and vendor behavior, with at least one example of taking an ambiguous memory failure to root cause and delivering a productized fix.
• Strong hands-on lab skills: oscilloscope, DMM, thermal chambers, protocol analyzers; practical understanding of PCB stack-up, board layout, power planes, and SI/PI implications for memory.
• Proven experience building or scaling AI-driven workflows for memory characterization, margin analysis, or failure triage with measurable impact on debug velocity, coverage, or escape rate.
• Ability to lead cross-functional debug and to produce reusable qualification methodology and playbooks.
• Excellent collaboration skills for working with globally distributed teams and external DRAM vendors.

Education Requirements

B.Tech or M.Tech in Electrical, Electronics, or Computer Engineering, or equivalent practical experience.

NVIDIA invests in employees with competitive benefits and learning opportunities.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.