The Memory PHY Power Architect position at Synopsys involves leading the design and development of power-efficient memory PHY architectures and creating optimization power models for memory subsystems. The role demands collaboration with cross-functional teams and mentoring of engineers, ensuring successful project outcomes.
Senior level, with 15+ years of experience in memory PHY architecture and power modeling.
Key responsibilities include:
Applicants must meet the following criteria:
A Bachelor of Science in Electrical Engineering (BSEE) or a Master of Science in Electrical Engineering (MSEE) is required.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
