Memory Layout Technical Lead
RenesasJob Title
Memory Layout Technical Lead
Role Summary
Lead layout design for non-volatile memory IP (Flash, MRAM, ReRAM) used in automotive, industrial, and IoT MCUs. Serve as the technical lead of the memory layout team, driving layout strategy, execution, verification, and cross-functional alignment.
Onsite role based in Kodaira, Tokyo, Japan.
Experience Level
Senior - typically 10+ years in non-volatile memory layout design with ~5+ years of leadership or review-leading experience.
Responsibilities
The primary responsibilities include:
- Lead the memory layout design team for mixed-signal non-volatile memory IP.
- Establish layout strategies from IP requirements and circuit specifications.
- Perform and oversee layout design and verification activities.
- Drive PPA (performance, power, area) optimization for MCU products.
- Coordinate development with domestic and international memory teams and circuit designers.
- Lead design reviews, reach technical alignment, and mentor engineers.
Requirements
Must-have and preferred qualifications:
- Must: 10+ years of hand-drawn layout design experience for non-volatile memory IP (Flash, MRAM, ReRAM).
- Must: 5+ years leading layout reviews and achieving alignment with circuit designers.
- Must: Experience collaborating in English with overseas partners.
- Nice-to-have: Place-and-route (P&R) experience.
- Nice-to-have: Analog circuit design experience.
- Nice-to-have: Experience using AI-assisted layout techniques or tools.
Education Requirements
Not specified.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
