Memory Interface PHY IP, Design Engineering Architect

Job Title

Memory Interface PHY IP, Design Engineering Architect

Role Summary

Provide technical leadership to define scalable, high-quality PHY IP architectures for memory interfaces (e.g., DDR, LPDDR). Translate standards and customer requirements into architecture decisions that reduce execution risk and accelerate customer engagements.

Work cross-functionally with design, verification, layout, silicon validation, sales, and program teams; serve as a customer-facing technical architect and influence product and technology roadmaps.

Experience Level

Senior — minimum 15 years of industry experience in memory interface PHY, high-speed I/O, or related domains (as specified in the posting).

Responsibilities

Key responsibilities include technical architecture, customer engagement, and cross-functional execution.

• Contribute to PHY architecture development for memory interface PHY IPs, covering electrical, timing, power, and protocol considerations.
• Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements.
• Provide deep understanding of PHY/IO circuit architecture, including TX/RX, clocking, termination, power delivery, and signal integrity trade-offs.
• Act as a customer-facing technical architect during pre-sales, evaluations, and post-delivery support, articulating architecture choices and trade-offs.
• Collaborate with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposals.
• Provide expert-level IP support to customers, including architecture clarification and feature customization.
• Work with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implemented.
• Review and guide architecture specifications, design reviews, and technical documentation.
• Identify future standards and protocol evolution to influence product and technology roadmap planning.
• Demonstrate clear communication, accountability, and technical ownership across internal and external interactions.

Requirements

Must-have skills and experience.

• Minimum 15 years of industry experience in memory interface PHY, high-speed I/O, or related domains.
• Strong background in memory interface PHYs, JEDEC standards, and related protocols.
• Proven ability to own customer-facing technical engagements and drive issues to closure.
• Excellent written and verbal communication skills.
• Deep technical knowledge of PHY/IO circuit trade-offs (signal integrity, termination, clocking, power delivery).

Education Requirements

Required: M.S. degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting). No alternative "equivalent experience" language was provided in the job text.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.