Memory Design Engineer
Allegro MicroSystemsJob Title
Memory Design Engineer
Role Summary
The Memory Design Engineer will design, verify, characterize, and validate standard memory IP (e.g., SRAM, ROM, EEPROM, OTP, FLASH, register files) and associated mixed-signal driver circuits for Allegro's semiconductor technology development. The role sits in Design Enablement within Technology Development and supports the global design community by delivering qualified memory IP and mask requirements.
Experience Level
Entry-level / Early career. Minimum 2 years of industry experience is required.
Responsibilities
Key responsibilities include design, verification, and validation of memory and digital IP, plus documentation and release activities for use by global design teams.
- Design NVM, volatile memory, driver circuits, and digital IP macros.
- Perform IP layout in EDA tools and coordinate macro floorplanning and layout design.
- Plan and execute silicon test, IP validation, and characterization.
- Standardize memory and digital IP for integration into custom PDKs and global reuse.
- Prepare and publish IP specifications and application use cases.
- Support memory debug and diagnostics with design teams.
Requirements
Must-have technical skills and experience for performing the role.
- Minimum 2 years industry experience in memory and mixed-signal transistor-level design, circuit verification, and silicon testing.
- Experience with digital components: logic, memory, EEPROM, TAP controllers, JTAG, FPGA, serial data protocols, microprocessors/microcontrollers.
- Ability to develop memory test/validation plans and characterize memory/standard cells in liberty format.
- Hands-on experience with Cadence and related EDA flows (Virtuoso, Genus, Innovus, Xcelium/Incisive/Xcellium, Modus Test, Quantus/Calibre) and IP characterization tools.
- Familiarity with HDL (Verilog, Verilog-A, Verilog-AMS); basic scripting and software skills.
- Experience with layout parasitic/leakage trade-offs and characterization for sub-micron technologies.
Nice-to-have:
- Skills in C and SystemVerilog; FPGA development experience.
- Understanding of device physics at the transistor level (STI, DTI, cross-sections) and modeling challenges.
Education Requirements
Bachelor of Science in Electrical Engineering (BSEE) is required. The posting specifies a minimum of 2 years of relevant industry experience.
About the Company
Company: Allegro MicroSystems
Headquarters: Manchester, New Hampshire, USA
Global semiconductor company with over 30 years of innovation, developing semiconductor devices and design enablement tools. Allegro focuses on device development, foundry partnerships, IP characterization, and design automation to support product roadmaps and technology advancement.
