Memory Design Engineer

Job Title

Memory Design Engineer

Role Summary

Design and develop single- and multiport SRAM and register-file compilers for advanced CMOS process nodes. Work covers circuit design and simulation, characterization and margin analysis, timing and signal/power integrity, and silicon debug to achieve yield and performance targets.

Experience Level

Mid-level. See Education Requirements for degree and years guidance.

Responsibilities

Primary responsibilities include design, verification, characterization, and silicon bring-up for high-speed memory IP.

• Design and develop single/multiport SRAM and register-file compilers in 28nm/16FF/7FF/5FF nodes.
• Circuit design and simulation of bitcell, wordline decoder, sense amplifier, column decoder, sample circuits and control logic.
• Develop characterization and critical-path flows for margin and detailed characterization simulations.
• Perform statistical analysis of bit-cell and sense-amplifier behavior for compiler-target yield sign-off.
• Tune designs, perform margin analysis, and sign off compilers to meet yield and performance targets.
• Run logic simulations and detailed timing analysis of key high-speed memory paths.
• Perform signal-integrity (EM) and power-integrity (IR drop) analysis and implement design mitigations.
• Participate in silicon debug, failure analysis, and fixes during bring-up.

Requirements

Key technical skills and practical experience required; items labeled as "Nice-to-have" are preferred but not mandatory.

• Must-have: Expertise in high-speed, low-power CMOS circuit design, including clocking schemes and static/dynamic logic.
• Must-have: Experience defining and driving memory compiler specifications through to final release.
• Must-have: Hands-on silicon debug and failure analysis experience.
• Must-have: Proficiency with schematic/layout editor tools (Cadence and/or Mentor).
• Must-have: Proficiency in circuit simulation and Monte Carlo/variation analysis tools (examples: HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewers).
• Must-have: Strong understanding of layout-related issues at advanced nodes (sub-nanometer/FinFET regimes).
• Must-have: Knowledge of power-architecture techniques such as split-rail and power-gating and related circuit implementation.
• Must-have: Ability to perform signal- and power-integrity (EM/IR) analysis.
• Nice-to-have: Scripting skills (Skill, Perl, Python) for automation.
• Nice-to-have: Familiarity with memory DFT and characterization flow development.

Education Requirements

Master's degree with 2+ years of relevant experience, or Bachelor's degree with 3+ years of relevant experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.