Memory Control Design Engineer

Job Title

Memory Control Design Engineer

Role Summary

Engineer on the QCT Memory Controller Design Team responsible for architecture, RTL design, and delivery of high-speed DDR memory controllers (LPDDR/PCDDR) used in Qualcomm products. The role focuses on front-end controller logic that interfaces to CPUs, DSPs, and multimedia processors and supports integration into full SoCs.

Experience Level

Mid-level — target experience range: 3–8 years in ASIC/memory-controller or related digital design work.

Responsibilities

Key responsibilities include design, implementation, and integration of memory controller IP and supporting tasks to bring IP into product:

• Define and drive micro-architecture and design specifications for portions of the memory controller front end.
• Implement and deliver RTL for controller logic and collaborate with verification engineers to ensure correctness.
• Debug RTL and integration issues in pre- and post-silicon contexts and provide integration support for system-level bring-up.
• Perform synthesis, timing closure, gate-level simulation support, power analysis, and interact with physical design teams.
• Contribute C/C++ modeling of memory controller behavior when required.
• Improve design methodology and flows to enhance productivity and quality.

Requirements

Must-have technical skills and experience:

• Experience with DDR controller architectures, especially front-end interfaces to CPU, DSP, and multimedia processors.
• Familiarity with x86 or ARM CPU and bus architectures.
• Proven RTL design and implementation experience; strong digital design fundamentals.
• Experience with synthesis, static timing analysis, timing closure, and physical-design interactions.
• Experience collaborating with verification teams; comfortable supporting gate-level simulations and debug flows.
• Experience with power analysis and delivering low-power designs.
• Ability to debug complex system integration issues and communicate findings to cross-functional teams.
• Target experience range: 3–8 years in relevant ASIC/memory-IP design roles.

Nice-to-have:

• C/C++ modeling experience for IP behavior and performance analysis.
• Prior work on high-frequency (>1 GHz) memory controller designs.

Education Requirements

One of the following: Bachelor's degree in Science, Engineering, or related field plus 2+ years ASIC design/verification/integration experience; OR Master's degree in Science, Engineering, or related field plus 1+ year ASIC design/verification/integration experience; OR PhD in Science, Engineering, or a related field.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.