Mask Layout Designer

Job Title

Mask Layout Designer

Role Summary

Design block, macro, and chip-level layouts and floorplans to meet project specifications and manufacturability requirements. Work within the Mask Layout Design team to produce accurate layouts, run verification, troubleshoot issues, and communicate status to internal and external stakeholders.

The role emphasizes technical leadership on mid- to large-sized projects, process and guideline development, and cross-team coordination with engineering, program management, and foundry partners.

Experience Level

Mid-level (typically 3–7 years). The posting requires experienced layout designers and expects independent work and some supervisory responsibility.

Responsibilities

Primary responsibilities include design, verification, process improvement, and team coordination:

• Lead development of complex layouts and floorplans from schematics and requirements.
• Define and implement layout guidelines, design rule manuals, and checklists.
• Manage testing and validation of top-level designs using layout and verification tools to ensure manufacturability.
• Analyze and troubleshoot design issues; provide technical sign-off and guidance to the team.
• Improve or automate layout and verification methods to increase team efficiency.
• Plan and re-scope projects, reassign resources, and manage project priorities and deliverables for multiple projects.
• Collaborate with internal teams and external stakeholders (e.g., PVERF, PDCAD, foundry teams) to resolve complex issues.
• Provide supervision and mentorship to direct reports and influence technical decisions.

Requirements

Must-have technical skills and experience; preferred items are listed separately.

• Proven experience designing custom layouts in relevant domains (analog, mixed-signal, RF, digital); see Education Requirements for degree/experience equivalencies.
• 4+ years using layout design and verification tools (examples: Cadence, LVS, rmap).
• Strong knowledge of layout techniques, PPA/yield considerations, and basic electronic principles (currents, parasitics, resistance).
• Ability to perform advanced analyses, debug complex issues, and provide technical sign-off.
• Clear verbal and written communication skills for diverse audiences, including senior leadership.
• Experience leading or supervising small teams and managing multiple projects or priorities.
• Nice-to-have: experience with specific process technologies (FINFET, CMOS, gate arrays), technical leadership experience, budget/project financial exposure, and interaction with senior leadership.

Education Requirements

Options listed in the posting: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field (with 4+ years layout experience); OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field (with 6+ years layout experience); OR High School diploma or equivalent (with 8+ years layout experience). Preferred: Master’s degree in Technology, Electrical Engineering, Electronic Engineering, or related field. Posting allows equivalent practical experience in lieu of formal degrees.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.