Manager / Senior Manager – Design Verification

Job Title

Manager / Senior Manager 6 Design Verification

Role Summary

Lead a multi-site Design Verification team responsible for IP and SoC verification across multiple projects. The role focuses on verification planning, execution, closure and on-time silicon delivery while improving verification methodology, automation, and team capabilities.

Experience Level

Senior level. Requires approximately 10 615 years of experience in design verification and proven experience leading verification teams.

Responsibilities

Accountable for verification delivery, technical leadership, and team development across programs.

• Lead and grow a high-performing verification team for IP and SoC projects.
• Plan and drive verification execution: test strategy, regressions, coverage closure, sign-off, and on-time delivery.
• Provide hands-on technical leadership in SystemVerilog/UVM, assertions, constrained-random and coverage-driven verification.
• Manage project priorities, risks, resources, and dependencies across multiple programs and sites.
• Collaborate with Design, Architecture, Firmware, Validation, and Program Management globally.
• Improve verification methodologies, automation, regression efficiency, and reusable infrastructure.
• Champion adoption of new techniques and tools, including AI-assisted workflows and formal methods where appropriate.
• Mentor engineers, develop technical leaders, and establish execution metrics to monitor progress and mitigate risks.
• Support hiring, performance management, and capability building for the verification organization.

Requirements

Must-have technical and leadership qualifications; preferred items listed separately.

• Must-have: 10 615 years in design verification with strong expertise in IP, subsystem, and SoC verification.
• Proven experience leading and developing verification teams in a multi-site development environment.
• Strong hands-on expertise in SystemVerilog, UVM, assertions, constrained-random verification, functional coverage, and regression management.
• Demonstrated track record delivering complex verification projects from planning through sign-off.
• Deep understanding of verification planning, testbench architecture, debug methodologies, and verification metrics.
• Experience driving verification methodology, automation, reuse, and productivity improvements across teams.
• Excellent leadership, problem-solving, communication, stakeholder management, and cross-functional collaboration skills.
• Nice-to-have: experience with formal verification, emulation, FPGA prototyping, hardware-software co-verification, low-power verification (UPF), AI-assisted verification, data analytics, and scripting (Python/Perl/Tcl).

Education Requirements

B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Computer Engineering, VLSI, or a related field (as listed in the source).

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.