Manager / Senior Manager – Design Verification

Job Title

Manager / Senior Manager – Design Verification

Role Summary

Lead and grow a Design Verification team in Hyderabad responsible for IP and SoC verification across multiple product programs. Drive verification strategy, planning, execution, coverage closure, and delivery while collaborating with design, architecture, firmware, validation, and program management teams globally.

Focus areas include verification methodology and automation, reusable infrastructure, debug and metrics, and adoption of advanced techniques such as formal methods and AI-assisted workflows.

Experience Level

Senior-level. Target experience: 10–15 years in design verification with demonstrated people and program leadership.

Responsibilities

Accountable for verification delivery, technical leadership, and team development across multiple projects.

• Lead and develop a high-performing design verification team for IP and SoC projects.
• Plan and drive verification execution, functional coverage closure, regression management, and sign-off.
• Provide hands-on technical leadership in SystemVerilog, UVM, assertions, constrained-random verification, and debug methodologies.
• Manage project priorities, technical risks, resource allocation, and inter-project dependencies.
• Collaborate with cross-functional teams across global sites to align verification and delivery plans.
• Define verification strategies for complex IPs, subsystems, and SoCs.
• Improve verification methodology, automation, regression efficiency, and reusable verification infrastructure.
• Champion adoption of new techniques and tools, including formal methods, emulation/FPGA prototyping, and AI-assisted workflows.
• Mentor engineers, develop technical leaders, and build a culture of accountability and continuous learning.
• Establish execution metrics, monitor progress, identify risks early, and drive issues to closure.

Requirements

Must-have technical skills and leadership experience to deliver complex verification programs.

Must-have:

• 10–15 years of design verification experience focused on IP, subsystem, and SoC verification.
• Proven experience leading and developing verification teams in multi-site environments.
• Strong hands-on expertise in SystemVerilog, UVM, assertions, constrained-random techniques, functional coverage, and regression management.
• Deep understanding of verification planning, testbench architecture, coverage closure, debug methodologies, and verification metrics.
• Experience driving methodology, automation, reuse, and productivity improvements across teams.
• Strong leadership, problem-solving, communication, stakeholder management, and cross-functional collaboration skills.

Nice-to-have:

• Experience with formal verification, emulation, FPGA prototyping, performance verification, or hardware-software co-verification.
• Knowledge of low-power verification methodologies (e.g., UPF) and multi-power-domain designs.
• Experience developing reusable UVM environments, verification IP, automation frameworks, and scalable regression infrastructure.
• Exposure to AI-assisted verification, data analytics, advanced debug tools, or scripting (Python, Perl, Tcl).

Education Requirements

B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Computer Engineering, VLSI, or a related technical field.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.