Manager CAD Engineering (f/m/d)

Job Title

Manager CAD Engineering (f/m/d)

Role Summary

Lead a small PDK/Physical Verification (PV) team to develop, maintain and release PV methodology, PDK components, QA systems and tools that support design teams and foundry interactions.

Work is EU-based and focuses on PDK development, PV flows, EDA tool integration, and tape-out support across analog and digital design groups.

Experience Level

Senior — management-level role. Preferred experience: approximately 10+ years in PDK, physical verification or related semiconductor engineering, including leadership or people-management experience where possible.

Responsibilities

Primary responsibilities include PDK/PV methodology development, tool/vendor interfacing, QA and tape-out support, and team leadership.

• Define, plan and drive company-wide Physical Verification methodology, flows and documentation.
• Maintain, update and improve PV QA systems and QA automation.
• Review, adapt and release foundry DRC/LVS/PEX/FILL rundecks and PDK components for internal customers.
• Develop, test and deploy in-house tools to address internal customer needs or EDA gaps.
• Interface with foundries and EDA vendors to resolve issues, drive enhancements and ensure timely PDK deliverables.
• Provide DRC/LVS/FILL and parasitic extraction support to analog and digital design teams and support tape-outs.
• Work closely with design, layout, packaging and foundry technology teams to implement project requirements and address PV issues.
• Manage a team of PV engineers: set priorities, assign tasks, track deliverables and ensure project support.

Requirements

Essential technical skills and domain experience required; additional items listed as desirable.

• Must-have: Deep knowledge of DRC, LVS, FILL and parasitic extraction tooling and scripting (SVRF/TVF and TCL) or PVS/Pegasus equivalents.
• Must-have: Strong knowledge of foundry PDK components (PCELL, CDF, tech files) and modern semiconductor design flows.
• Must-have: Strong debugging capability across PV flows and toolchains; experience supporting tape-outs on demand.
• Must-have: Proficiency with UNIX shell, shell scripting, makefiles and either Perl or Python.
• Nice-to-have: Experience with Calibre PERC (P2P/CD), RDSON/EMIR commercial flows and PDK QA automation.
• Nice-to-have: Familiarity with Cadence Virtuoso custom IC platform (Virtuoso-L/XL), schematic capture and layout concepts.
• Nice-to-have: Prior management experience leading engineering teams.

Education Requirements

Preferred: Master’s degree in Electrical Engineering or equivalent; many team members hold MS/PhD. The posting cites a Master’s with ~10 years' experience as desirable and allows equivalent practical experience. Relevant fields: Electrical Engineering, Semiconductor Physics. No specific certifications required.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.