LEC CAD Engineer

Job Title

LEC CAD Engineer

Role Summary

The LEC CAD Engineer will develop, maintain, and operate Logical Equivalence Check (LEC) flows and tooling within the Global CAD (GCAD) organization to ensure functional equivalence across RTL, synthesis, and final gate representations for complex SoC designs.

You will collaborate with design, synthesis, implementation, and verification teams to debug non-equivalences, automate LEC runs, qualify EDA tool releases, and improve LEC methodology across Cadence Conformal and Synopsys Formality platforms.

Experience Level

Mid-level. The posting requests hands-on CAD/LEC experience (entry from ~1 year, with minimum-qualification variants up to 3+ years depending on degree).

Responsibilities

Primary responsibilities include ownership of LEC flows, debugging, automation, and cross-team coordination:

• Own and execute end-to-end LEC flows: RTL-to-initmap, RTL-to-initopt, RTL-to-finalopt, gate-to-gate, and ECO verification runs.
• Debug and resolve Non-Equivalences (NEQs), aborts, unmapped points, and incomplete verifications in complex SoC subsystems.
• Develop and maintain LEC scripts, dofiles, and automation using Tcl, Perl, Python, or Shell.
• Integrate LEC into synthesis flows via Cadence Genus and Synopsys DC interfaces.
• Support power-aware formal verification using UPF/CPF flows and Conformal Low Power or equivalent tools.
• Triage LEC-related tickets, provide technical guidance, and mentor engineers on methodology and debug techniques.
• Participate in design handoffs, sign-offs, cross-functional reviews, and vendor/tool qualification activities.

Requirements

Must-have technical skills and tools experience; listed as concise must-have vs nice-to-have.

• Must-have: Hands-on experience with Cadence Conformal LEC and Synopsys Formality for RTL-to-gate, gate-to-gate, and ECO verification.
• Must-have: Strong understanding of ASIC design flows (synthesis, P&R, ECO) and experience debugging NEQs and aborts in hierarchical designs.
• Must-have: Proficient scripting (Tcl, Perl, Python, Shell) and experience with UNIX/Linux and compute grid systems (LSF, SGE).
• Must-have: Familiarity with RTL languages (SystemVerilog/Verilog/VHDL) and knowledge of DFT impacts on LEC.
• Must-have: Experience with power-aware LEC (UPF/CPF) and Conformal Low Power or equivalent.
• Nice-to-have: Experience with Sequential Equivalence Checking (e.g., JasperGold SEC, Synopsys VC Formal), Smart LEC, SVP operators, advanced abort resolution, and FEQOR-style handoff/sign-off processes.
• Nice-to-have: Experience evaluating and qualifying new EDA tool releases and multi-tool LEC strategies.

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, VLSI & Embedded Systems or equivalent. Preferred: Master’s degree in Electrical Engineering, Computer Engineering, or VLSI & Embedded Systems. Minimum-qualification variants in the posting specify equivalence options: Bachelor's + 3+ years, Master’s + 2+ years, or PhD + 1+ year of relevant hardware engineering experience. Equivalent practical experience is accepted as stated.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.