Leadership Role - DFT

Job Title

Principal Member of Technical Staff (DFT) — Leadership Role

Role Summary

Lead ATPG strategy, implementation, and pattern validation for multi-million-gate SoCs within the IODC SoC DFT organization. Own ATPG execution from architecture through pre-silicon verification, tester enablement, silicon bring-up, and manufacturing ramp.

Work cross-functionally with RTL, DFT RTL, DFT verification, physical design, product engineering operations (PEO), ATE, and silicon validation teams to deliver production-quality test solutions and ensure test readiness.

Experience Level

Senior — preferred 16+ years of experience in SoC DFT and ATPG execution; demonstrated leadership of ATPG delivery for high-volume SoC products.

Responsibilities

Primary responsibilities include:

• Own end-to-end ATPG execution for large-scale SoCs from architecture through production test.
• Define ATPG methodologies, test strategies, coverage closure plans, and pattern signoff criteria.
• Generate and validate scan, transition-fault, cell-aware, bridge, chain-diagnosis, and compression-based ATPG patterns.
• Drive pattern validation across simulation, emulation, ATE, and platform environments and lead tester correlation activities.
• Collaborate with DFT RTL, DFT verification, RTL, physical design, timing, PEO, and ATE teams to ensure robust DFT implementation and tester readiness.
• Perform root-cause analysis and resolve ATPG, tester, silicon, and yield-related issues; support silicon bring-up and production ramp.
• Optimize pattern quality, tester efficiency, and test cost; develop automation and AI-enabled flows to improve productivity.
• Mentor engineers, drive best practices, and lead technical initiatives across distributed teams.

Requirements

Required and preferred technical skills and experience.

• Must-have: Extensive practical experience in SoC DFT and ATPG execution for multi-million-gate SoCs, including ownership of ATPG delivery for production products.
• Must-have: Strong experience with pattern generation and validation (scan, transition-fault, cell-aware, compression, diagnosis) and tester/ATE correlation.
• Must-have: Hands-on experience debugging silicon failures and supporting yield-improvement activities; working knowledge of semiconductor manufacturing test flows and production deployment.
• Must-have: Strong scripting and automation skills (Python, Perl, Tcl, Shell, or similar) and experience building automation flows for ATPG and debug.
• Must-have: Proven ability to lead cross-functional, geographically distributed teams and drive technical execution from design to manufacturing.
• Preferred: Deep knowledge of scan architecture, compression techniques, LBIST/MBIST, boundary scan, and physical-aware ATPG/DFT timing.
• Preferred: Experience with pattern formats and conversion flows (STIL, WGL) and tester pattern formats; familiarity with power-aware ATPG and coverage optimization.
• Preferred: Familiarity with ATPG tools such as Tessent, Modus, TestMAX, TetraMAX or equivalent.

Education Requirements

Bachelor's or Master's degree in a related discipline preferred.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.