Lead STA Engineer

Job Title

Lead STA Engineer

Role Summary

The Lead STA Engineer will own static timing analysis (STA) methodology and timing convergence for IP, subsystem, and full‑chip designs implemented in advanced FinFET process nodes. This hands‑on role sits in the hardware engineering team and focuses on signoff flows, correlation, and timing quality for low‑power, high‑frequency designs.

The position requires close cross‑functional collaboration with RTL, DFT, physical design, IP vendors, and post‑silicon bring‑up teams to ensure robust timing closure and pre‑to‑post silicon correlation.

Experience Level

Level: Senior. Typical guidance: 5+ years of industry experience in STA and timing convergence (senior/lead level responsibilities).

Responsibilities

Primary responsibilities include owning timing methodology, driving signoff, and improving timing flows and correlation.

• Develop and maintain timing flows and methodology for FinFET and multi‑patterning technologies using tools such as Cadence Tempus or Synopsys PrimeTime.
• Drive timing convergence and signoff for IP blocks, subsystems, and SoC level designs.
• Define timing margining, corner/voltage definitions, extraction methodology, and SYN/PNR correlation for signoff.
• Develop checks for slew rate, glitch/noise, and other timing integrity criteria.
• Create custom timing checks specific to the company’s ultra‑low‑power architecture.
• Collaborate with RTL, DFT, and IP vendors to define SDC constraints and ensure correct handoffs.
• Maintain and verify timing collateral for all hard and soft IP used in designs.
• Partner with post‑silicon bring‑up teams to validate pre‑si to post‑si timing correlation.
• Coordinate third‑party timing vendor work and integrate their deliverables into internal flows.
• Continuously improve flow consistency and efficiency across multiple product swim lanes.

Requirements

Must‑have technical skills and experience; listed below are required skills first, followed by desirable skills.

• Must have: Proven track record of STA sign‑off for IP/Subsystem/SoC across multiple tape‑outs in 12nm or below process nodes.
• Must have: Practical experience with EDA STA and simulation flows (Cadence, Synopsys, Mentor tooling; PrimeTime, HSpice) and hierarchical design/abstraction techniques.
• Must have: Hands‑on timing convergence experience for both high‑frequency and low‑power designs and understanding of timing vs. power tradeoffs.
• Must have: Expert knowledge of static timing analysis: constraints, exceptions, corners/voltage definitions, and timing margining.
• Must have: Strong scripting skills (TCL, shell, Python) for flow automation and custom checks.
• Nice to have: Knowledge of computer architecture, physical design and ASIC implementation, full‑chip sign‑off budgeting.
• Nice to have: Familiarity with circuit design, device physics, deep sub‑micron and SOI technology implications to physical design.
• Nice to have: Experience integrating analog or mixed‑signal macros and building CAD flow infrastructure for physical design engineers.

Education Requirements

Master's degree in Electrical Engineering with 5+ years of industry experience, or PhD in Electrical Engineering with 3+ years of industry experience.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.