Lead STA Engineer

Job Title

Lead STA Engineer

Role Summary

Lead STA Engineer responsible for driving static timing analysis and timing closure for block- and full-chip designs. Works within the signoff/timing team and partners with Synthesis, CTS, Physical Design and Design teams to achieve signoff readiness and tape-out milestones.

Experience Level

Senior-level. Requires approximately 15+ years of experience in static timing analysis and timing-closure for block and full-chip designs.

Responsibilities

Primary responsibilities include timing analysis, constraint development, cross-team debugging, and ECO-driven timing closure.

• Perform full-chip and block-level static timing analysis (STA) across all modes and corners, pre- and post-layout.
• Develop, validate, and maintain timing constraints and SDC files for signoff readiness.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal-integrity timing violations.
• Drive timing closure through ECO implementation and timing optimizations in collaboration with PD, Synthesis, CTS, and RTL teams.
• Perform variation-aware analysis for process, voltage, and temperature (OCV/AOCV/POCV, derates, MMMC).
• Support low-power timing and UPF/CPF-aware STA; perform SI-aware, crosstalk, and IR-drop-aware timing analysis.
• Generate timing reports, lead cross-functional timing reviews, and report closure status to stakeholders.

Requirements

Must-have:

• Extensive hands-on experience with industry STA tools (for example Synopsys PrimeTime or Cadence Tempus).
• Deep knowledge of static timing concepts: SDC, timing exceptions, false paths, multicycle paths, clock tree design, uncertainty, latency, skew, and jitter.
• Strong scripting skills in Tcl, Perl, or Python and experience with automation and flow development.
• Proven ability to analyze and resolve timing violations independently and lead timing closure activities.
• Experience with timing closure techniques, ECO methodologies, and cross-functional collaboration with PD, RTL, and signoff teams.
• Familiarity with advanced process nodes and variation-aware signoff methodologies.

Nice-to-have:

• Experience with SI-aware timing, crosstalk analysis, and IR-drop-aware timing closure.
• Experience in low-power timing analysis and UPF/CPF-aware STA.

Education Requirements

Not specified.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.