Lead Solutions Engineer — Runset Enablement (Physical Verification)

Job Title

Lead Solutions Engineer — Runset Enablement (Physical Verification)

Role Summary

Lead hands-on development, validation, and automation of Pegasus DRC and LVS runsets for advanced semiconductor process nodes. Work closely with customers, R&D, and cross-functional teams to deliver reliable physical verification solutions and support timely product deliveries in U.S. time zones.

Experience Level

Senior role. Seeks an experienced engineer with substantial hands-on runset and verification delivery experience; see Education Requirements for degree and years guidance.

Responsibilities

Deliver and support high-quality physical verification runsets and related automation; provide customer enablement and collaborate across teams.

• Develop, validate, and maintain Pegasus DRC and LVS runsets for advanced nodes.
• Design and maintain automation frameworks for regression execution, issue detection, and validation reporting.
• Debug verification issues with R&D and cross-functional teams; validate fixes and improve performance.
• Provide technical enablement and support to customers on tool usage and verification methodologies.
• Apply and refine best practices for runset development, validation, and quality assurance.
• Work independently on complex technical deliverables and provide guidance to the team.
• Coordinate with internal teams to support predictable and timely solution delivery.

Requirements

Necessary technical skills and practical experience for successful performance in this role.

• Proven hands-on experience developing and validating DRC and LVS runsets using Pegasus or comparable tools (Calibre, ICV, Assura).
• Experience building or maintaining automation for regression, validation, and reporting.
• Proficiency in TCL, Python, and/or Perl; experience in Linux/Unix environments.
• Solid understanding of physical verification methodologies and advanced process challenges (ground rules, fill, ESD, multi-die designs).
• Familiarity with chip fabrication processes and advanced-node verification issues.
• Strong problem‑solving, technical execution, and communication skills; ability to collaborate across global teams and take ownership of tasks.
• Nice-to-have: Experience with PERC and Fill runsets.

Education Requirements

MS degree with 5+ years of relevant experience, or PhD with 3+ years, in Electrical Engineering, Computer Science, or a related technical field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.