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Lead Software Engineer

Cadence Design Systems
May 20, 2026
Full-time
On-site
San Jose, California, United States
$114,800 - $213,200 USD yearly
EDA Jobs, Level - Senior

Job Title

Lead Software Engineer

Role Summary

Responsible for design, development, and validation of PCIe Verification IP within the VIP team. Lead engineering efforts to deliver reusable, robust verification software used in SoC and protocol verification flows. Collaborate across multi-site teams and with technical support and customers to resolve integration and usage issues.

Experience Level

Senior. The posting specifies degree-plus-experience: BS + 4 years, MS + 2 years, or new PhD graduate.

Responsibilities

Primary duties include software development, validation, cross-site collaboration, and customer-facing problem resolution for Verification IP products.

  • Design, implement, and validate PCIe Verification IP software and related components.
  • Develop reusable, maintainable C/C++ code using object-oriented design and sound software practices.
  • Translate customer use models and protocol specifications into product features and verification capabilities.
  • Collaborate with distributed development teams; contribute to technical roadmap and milestones.
  • Mentor and train engineers to support product delivery and team growth.
  • Work with technical support and key customers to diagnose and resolve integration and usage issues in diverse verification environments.

Requirements

Must-have technical skills and abilities:

  • Proven experience modeling in C/C++ with strong object-oriented design, algorithms, and data-structure skills.
  • In-depth understanding of time/space complexity and advanced debugging techniques for large codebases.
  • Strong analytical and problem-solving skills; ability to visualize processes and outcomes.
  • Outstanding written and verbal communication and ability to work collaboratively across locations.
  • Experience working in a multi-location or distributed development environment.

Nice-to-have:

  • Working knowledge of PCI Express (PCIe) or other protocols (USB, NVMe, SATA, DisplayPort).
  • Familiarity with Verilog/SystemVerilog and OVM/UVM verification methodologies.
  • Experience with digital logic design or IP/SoC-level verification flows.
  • Familiarity with EDA tool flows and customer-oriented support.

Education Requirements

Bachelor's degree (BS) with a minimum of 4 years' relevant experience, or Master's degree (MS) with a minimum of 2 years' relevant experience, or a recent PhD graduate. No specific field of study or explicit equivalent-experience language is listed in the posting.


About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.

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Date Posted: 2026-05-20