Lead Software Engineer

Job Title

Lead Software Engineer

Role Summary

Own the design, development, validation, and delivery of Assertion-Based Formal Verification IPs, including Verilog design models and SystemVerilog Assertions for industry-standard protocols. Work with distributed teams to meet delivery commitments and support customer-facing technical discussions when required.

This role focuses on technical execution and quality of formal verification IPs with an emphasis on automation, scalability, and verification completeness.

Experience Level

Senior role. Typical experience expectation: around 5+ years of RTL design/verification experience; candidates with an advanced technical degree may be considered with ~3+ years of experience.

Responsibilities

Primary responsibilities include owning technical delivery of assertion-based verification IPs and ensuring verification completeness and release readiness.

• Design, implement, validate, and maintain Assertion-Based Verification IPs for industry-standard protocols.
• Analyze protocol specifications and translate requirements into formal verification plans, assertions, assumptions, and coverage goals.
• Develop synthesizable RTL and verification components using Verilog/SystemVerilog and SV-RTL concepts.
• Apply formal verification methodologies to prove protocol properties and address convergence challenges with appropriate abstractions and constraints.
• Create verification plans, define measurable coverage targets, review results, and close functional and formal coverage gaps.
• Debug complex design and verification failures, perform root-cause analysis, and deliver scalable solutions using EDA tools.
• Build and enhance automation, regression, and productivity flows using scripting (Python, Tcl).
• Provide technical guidance via design and code reviews, mentor junior engineers, and improve verification methodology and processes.
• Collaborate with Application Engineering and cross-site teams to resolve technical issues and communicate risks, dependencies, and progress to stakeholders.

Requirements

Must-have technical skills and experience to perform the role.

• Several years of RTL design and verification experience (see Experience Level for guidance).
• Strong Verilog/SystemVerilog skills and experience with SV-RTL design or verification.
• Experience with verification planning and coverage-driven verification.
• Proficiency in scripting for automation and regression (Python and/or Tcl).
• Practical experience with at least one protocol such as AXI, CHI, PCIe, or CXL.
• Ability to debug complex issues with EDA tools and perform root-cause analysis.
• Strong written, verbal, and presentation skills; ability to work with customers and cross-functional teams.
• Demonstrated ownership, sound technical judgment, and ability to drive assignments from planning through delivery.
• Mentoring and code-review experience; ability to improve team processes and verification methodology.

Nice-to-have:

• Familiarity with formal verification concepts and tools.
• Working knowledge of AI/ML concepts and experience using AI-assisted tools to improve verification, debugging, or automation.

Education Requirements

Degree preferences listed in the source: BE/BTech/ME/MS/MTech in Electrical/Electronics. The posting indicates typical experience expectations tied to degree level (e.g., ~5+ years for bachelor's holders; ~3+ years for master's holders). No certifications were specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.