Lead RTL Verification Engineer
SynopsysJob Title
Lead RTL Verification Engineer
Role Summary
The Lead RTL Verification Engineer will be responsible for verifying RTL designs within the ASIC Digital Design category. This role plays a critical part in ensuring the quality and functionality of design implementations.
Experience Level
Mid-level with prior experience in RTL verification assumed.
Responsibilities
The Lead RTL Verification Engineer will perform the following key responsibilities:
- Develop and execute verification plans for RTL designs.
- Utilize simulation tools and methodologies to validate design functionality.
- Collaborate with design teams to ensure alignment on expectations and outcomes.
- Identify and debug issues within the verification process.
- Document verification results and provide feedback on design improvements.
Requirements
Essential qualifications include:
- Strong experience in RTL verification methodologies (e.g., SystemVerilog, UVM).
- Proficient in simulation tools used for RTL verification.
- Knowledge of digital design principles and ASIC design flows.
Education Requirements
Bachelor's degree in electrical engineering or a related field is expected.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
