Lead RTL Engineer - Mixed-Signal IPs
Silicon LabsJob Title
Lead RTL Engineer - Mixed-Signal IPs
Role Summary
Design, integrate, and verify digital RTL blocks for mixed-signal IPs (ADC/DAC interfaces, PLL control, power management, sensor front-ends) and enable their integration into SoCs. Work closely with analog designers, system architects, verification, and SoC teams to deliver synthesis-ready, low-power, and functionally robust IP.
Experience Level
Senior - typically 5–10 years of experience in digital RTL design with exposure to mixed-signal IP or subsystem development.
Responsibilities
Primary responsibilities include RTL development, verification collaboration, and SoC-level integration for mixed-signal IPs.
- Develop synthesizable RTL for mixed-signal IPs (ADC/DAC interfaces, PLL/DLL control, PMU logic, sensor front-ends).
- Define and implement digital-analog interface specifications and control logic in collaboration with analog engineers.
- Create behavioral models, run simulations, and perform co-verification with analog components to validate functionality and performance.
- Participate in micro-architecture and design reviews; document IP functionality and timing interfaces.
- Perform lint, CDC, RDC, and synthesis readiness analyses to ensure design quality.
- Work with verification engineers to define test plans, drive coverage closure, and debug cross-domain issues.
- Integrate mixed-signal IPs into SoC top-level RTL and resolve functional or timing problems during full-chip validation.
- Improve design methodologies, automation scripts, and reuse strategies for mixed-signal IP development.
Requirements
Required technical skills and experience. Education specifics are listed under Education Requirements.
Must-have:
- Proficiency in Verilog/SystemVerilog and RTL coding best practices.
- Experience with synthesis flows and static verification (lint, CDC/RDC analysis).
- Understanding of analog/mixed-signal concepts: sampling, clocking, calibration, and power management.
- Familiarity with digital communication protocols (SPI, I2C, APB, AXI).
- Scripting experience for automation (Python, TCL, Perl).
- Experience working in cross-functional teams (analog, verification, SoC integration) and strong debugging skills.
Nice-to-have:
- Hands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS).
- Experience with AI-powered tools to improve productivity and analysis.
- Prior experience integrating mixed-signal IPs into complex SoCs.
Education Requirements
B.E. / B.Tech or M.S. / M.Tech in Electrical Engineering, Electronics, or Computer Engineering.
About the Company
Company: Silicon Labs
Headquarters: Austin, Texas, USA
Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.
