Lead RTL Engineer, Mixed-Signal IPs

Job Title

Lead RTL Engineer, Mixed-Signal IPs

Role Summary

The Lead RTL Engineer will design, integrate, and verify digital RTL blocks for mixed-signal IPs (ADC/DAC interfaces, PLL/DLL control, power management, sensor front-ends) and enable their integration into SoCs. The role requires close collaboration with analog designers, system architects, verification teams, and SoC integration teams.

Experience Level

Senior-level. The posting requests approximately 5–10 years of experience in digital RTL design with exposure to mixed-signal IP or subsystem development.

Responsibilities

Primary responsibilities include RTL development, verification collaboration, and SoC integration of mixed-signal IPs.

• Develop synthesizable, synthesis-ready RTL (Verilog/SystemVerilog) for mixed-signal IP digital blocks.
• Define and implement digital-analog interface control logic and communication protocols with analog teams.
• Create behavioral models, run simulations, and perform co-verification with analog components.
• Participate in micro-architecture and design reviews; document IP functionality and timing interfaces.
• Perform lint, CDC, RDC, and synthesis readiness checks and resolve issues.
• Work with verification engineers to define test plans, close coverage, and debug cross-domain issues.
• Integrate IP into SoC top-level RTL and address functional and timing problems during full-chip validation.
• Improve design methodologies, automation scripts, and reuse strategies for mixed-signal IP development.

Requirements

Must-have technical skills and experience; followed by useful additions.

• Must-have: 5–10 years of digital RTL design experience with strong Verilog/SystemVerilog skills and experience with synthesis and static verification flows (lint, CDC).
• Must-have: Familiarity with analog/mixed-signal concepts such as signal sampling, clocking, calibration, and power management.
• Must-have: Practical experience with digital communication protocols (SPI, I2C, APB, AXI) and working in cross-functional teams (analog, verification, SoC integration).
• Must-have: Scripting for automation (Python, Perl, TCL) and strong debugging and problem-solving skills.
• Nice-to-have: Hands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS) and exposure to low-power IP design.
• Nice-to-have: Experience using AI-powered tools to improve productivity, analysis, or decision-making.

Education Requirements

B.E. / B.Tech or M.S. / M.Tech in Electrical Engineering, Electronics, or Computer Engineering.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.