Lead RTL Design & Validation Engineer (DDR Protocols)

Job Title

Lead RTL Design & Validation Engineer (DDR Protocols)

Role Summary

Design, implement and validate RTL, firmware and calibration algorithms for AMD's DDR memory IPs and custom IP projects. Work with silicon design, verification, firmware and system teams to deliver reliable memory initialization, training and system bring-up.

Experience Level

Senior-level engineer. The posting indicates experience guidance of 9+ years (preferred); an academic-credentials line also references 12+ years.

Responsibilities

Primary responsibilities focus on DDR memory controller calibration, firmware, algorithm development and system-level validation.

• Design and implement firmware for DDR memory controller calibration across DDR standards.
• Develop and refine calibration algorithms to improve accuracy, convergence speed and adaptability across PVT variations.
• Create and execute validation plans for calibration firmware, algorithms and custom IPs; perform system-level bring-up and debug.
• Collaborate with silicon design, verification and system engineering to ensure hardware/firmware alignment and interoperability.
• Investigate and resolve memory training, initialization and stability issues during bring-up.
• Monitor emerging DDR technologies and propose improvements to calibration robustness and boot time.

Requirements

Must-have technical skills and practical experience; nice-to-have items noted separately.

• Must-have: RTL design experience in Verilog/SystemVerilog for digital blocks.
• Must-have: Practical experience implementing DRAM/memory controller initialization code and DDR PHY training/calibration software.
• Must-have: Working knowledge of C; embedded development experience is beneficial.
• Must-have: Understanding of memory technologies (DDR4, DDR5, LPDDR) and JEDEC standards.
• Must-have: Familiarity with system-level architecture and buses (e.g., AXI/AHB) and integration with system validation environments.
• Must-have: Experience with version control systems such as Perforce, ICManage or Git.
• Must-have: Practical STA/timing awareness and experience with timing closure tools.
• Nice-to-have: Experience with lab equipment (high-speed scopes, compliance packages, logic analyzers) and hands-on debug.
• Nice-to-have: Prior exposure to memory controllers and PHYs from multiple IP vendors.
• Strong written and verbal communication skills; experience working in geographically dispersed teams.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering (B.E./B.S., M.E./M.S., M.Tech) is specified. The posting references preferred/expected experience levels alongside these degrees (9+ years in preferred experience; an academic-credentials line notes 12+ years).

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.