Lead RTL Design Engineer - Mixed-Signal IPs

Job Title

Lead RTL Design Engineer - Mixed-Signal IPs

Role Summary

Develop, integrate, and verify synthesizable digital RTL for mixed-signal IPs and subsystems, working closely with analog designers, system architects, and SoC integration teams. Deliver high-quality, low-power, synthesis-ready RTL that interfaces reliably with analog components and the SoC top level.

Experience Level

Senior — typically 5–10 years of experience in digital RTL design with mixed-signal exposure.

Responsibilities

Primary responsibilities include design, verification, integration, and cross-team collaboration.

• Write synthesizable Verilog/SystemVerilog RTL for mixed-signal IPs (ADC/DAC interfaces, PLL/DLL control, PMU, sensor front-ends).
• Collaborate with analog engineers to define digital-analog interface specs, control logic, and protocols.
• Perform behavioral modeling, simulation, and co-verification with analog components to ensure functional correctness.
• Participate in micro-architecture and design reviews; document IP functionality and timing interfaces.
• Run design quality checks including lint, CDC/RDC, and synthesis readiness analyses.
• Work with verification teams to define test plans, drive coverage closure, and debug cross-domain issues.
• Integrate IP into SoC top-level RTL and resolve functional or timing issues during full-chip validation.
• Improve design methodologies, automation scripts, and reuse strategies for mixed-signal IP development.

Requirements

Must-have skills and relevant experience; nice-to-have items listed separately.

• Must-have: 5–10 years in digital RTL design with demonstrable mixed-signal or subsystem experience.
• Must-have: Proficiency in Verilog/SystemVerilog and familiarity with synthesis flows and static checks (lint, CDC).
• Must-have: Understanding of analog/mixed-signal concepts such as sampling, clocking, calibration, and power management.
• Must-have: Knowledge of digital communication protocols (SPI, I2C, APB, AXI).
• Must-have: Scripting experience (Python, TCL, Perl) for automation and flow improvements.
• Must-have: Experience working cross-functionally with analog, verification, and SoC integration teams.
• Nice-to-have: Hands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS, etc.).
• Nice-to-have: Familiarity with AI-powered tools that enhance productivity and analysis.

Education Requirements

B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.