Lead RTL Design Engineer

Job Title

Lead RTL Design Engineer

Role Summary

Lead front-end RTL engineer responsible for designing and integrating high-performance, power-efficient IP for the next-generation Cerebras Wafer Scale Engine (WSE). You'll drive RTL architecture, implementation, and integration while coordinating with verification, physical design, software, system teams, and external ASIC vendors to deliver chips from concept to production.

This is a hands-on technical leadership role focused on delivering silicon with strong PPA targets and production-quality RTL.

Experience Level

Level: Senior. Typical experience: 8–15 years delivering complex, high-performance RTL and multiple silicon projects.

Responsibilities

Primary responsibilities include architecture, RTL development, integration, and cross-functional coordination:

• Define functional specifications and micro-architecture; implement, review, and deliver RTL and synthesis-ready code.
• Manage and coordinate work with external ASIC vendors through the product development cycle.
• Collaborate with physical design to meet power, performance, and area (PPA) goals and drive design closure.
• Work with design verification and DFT teams to achieve required functional and test coverage.
• Integrate third-party IP and perform front-end chip integration tasks.
• Collaborate with software and system teams to optimize performance and enable product features.
• Debug silicon-level functional, timing, and power issues during bring-up.

Requirements

Must-have technical skills and experience; items below are required unless noted as nice-to-have.

• Proven track record of multiple silicon successes and delivering complex, high-quality RTL designs.
• Deep RTL design and front-end integration experience, including synthesis and delivering PPA-driven designs.
• Experience managing or collaborating with external ASIC vendors.
• Experience designing and integrating high-speed IO and SerDes technology; knowledge of PCIe and CPU interfaces.
• Networking protocol experience, including TCP/IP, RDMA, and Ethernet.
• Familiarity with debugging silicon functional, timing, and power issues.
• Proficient with scripting for design automation (Python, TCL).
• Nice-to-have: FPGA toolchain experience, place-and-route, floorplanning, and timing analysis.
• Able to work in a hybrid work environment.

Education Requirements

Master's degree in Computer Science, Electrical Engineering, or a closely related field, or equivalent practical experience.

Compensation: Base salary range: $175,000–$275,000 per year (actual compensation may include bonus and equity and will be determined by experience and qualifications).

Cerebras is an equal opportunity employer that values diversity. Information about privacy practices is available from the employer.

About the Company

Company: Cerebras

Headquarters: Sunnyvale, CA, USA

Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.