Lead RTL Design Engineer

Job Title

Lead RTL Design Engineer

Role Summary

Lead RTL engineer responsible for microarchitecture definition and RTL implementation across the dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and peripheral IP integration for a power-efficient SoC.

Work from architecture specification through synthesis-ready RTL, collaborating with architects, microarchitects, DV leads, physical design, and firmware teams to support tape-out and silicon bring-up.

Experience Level

Senior — 8+ years of RTL design experience with tape-out ownership on processor or accelerator SoCs.

Responsibilities

Primary responsibilities include defining microarchitecture, implementing RTL, and driving system integration and power optimization.

• Own microarchitecture definition for processor and compute units: dataflow pipelines, execution units, interfaces, and PPA targets.
• Design on-chip interconnects/NoC and data movement, coordinating with physical design for performance and scalability.
• Define memory subsystem interfaces, data movement, ordering, and synchronization.
• Architect configuration, scheduling, and execution models for multi-kernel workloads and host interaction.
• Drive power architecture and low-power RTL strategies (clocking, reset, power domains, retention logic).
• Collaborate with compiler and software teams for HW/SW co-design and workload mapping.
• Author uArch specifications and lead design reviews with architects, DV, and physical-design stakeholders.
• Mentor RTL engineers; review RTL for microarchitectural risks, coding style, and lint cleanliness.
• Participate in PPA analysis: synthesize blocks, review area/timing/power reports, and make tradeoffs.
• Support DV planning and silicon bring-up, including DFT/ATPG guidance and RTL-level debug during lab validation.

Requirements

Must-have technical skills and experience:

• 8+ years RTL design experience with tape-out ownership of dataflow-based design, on-chip networks, memory subsystems, or peripheral integration on processor or accelerator SoCs.
• Expert in SystemVerilog for synthesis-clean, lint-clean, timing-aware RTL; able to design complex state machines, arbiters, token controllers, and datapath logic from scratch.
• Strong understanding of parallel execution models (dataflow, SIMD, systolic arrays) and producer-consumer synchronization.
• Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped registers.
• Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic.
• Familiarity with at least one bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level.
• Experience taking RTL through synthesis and timing closure; able to read and act on SDC constraints, STA reports, and synthesis QoR summaries.
• Strong written communication skills; able to produce uArch specs and design review material independently.
• Experience with memory compiler toolchains.

Nice-to-have:

• Prior RTL ownership of NPUs, dataflow engines, or streaming DSPs with token-based flow control.
• Experience co-designing with compiler or graph-optimization teams and familiarity with ONNX/TFLite graph formats.
• Familiarity with NVM controller RTL (MRAM, RRAM) including ECC and program/erase sequencing.
• Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby) and relevant RTL choices.
• Exposure to functional safety standards (ISO 26262, IEC 61508) or formal verification for flow-control and deadlock freedom.
• Tape-out credits on edge-AI, IoT, or wearable SoCs at 12 nm or below.

Education Requirements

Not specified.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.