Lead RTL Design Engineer

Job Title

Lead RTL Design Engineer

Role Summary

Lead RTL engineer responsible for defining microarchitecture and delivering synthesis-ready RTL for a power-efficient SoC. Work spans dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and peripheral integration.

Collaborate with architects, microarchitects, DV, physical design, and firmware teams from spec through tape-out to meet aggressive power, performance, and area goals. Onsite roles available in Austin, TX; Pittsburgh, PA; and San Jose, CA.

Experience Level

Senior — requires substantial prior experience. The posting requests 8+ years of RTL design experience and tape-out ownership.

Responsibilities

Own microarchitecture and RTL delivery for assigned blocks and lead cross-functional integration.

• Define processor and compute-unit microarchitecture, set PPA targets, and drive implementation trade-offs.
• Design and implement on-chip interconnects and data-movement across the fabric in collaboration with physical design.
• Specify memory-subsystem interfaces, data ordering, synchronization, and banking models.
• Architect configuration, scheduling, and execution models for multi-kernel workloads and host interaction.
• Drive RTL-level low-power schemes: clocking, reset, power domains, retention, and UPF-driven flows.
• Author uArch specifications and lead design reviews with stakeholders including compiler, DV, and PD.
• Mentor and review RTL from senior and junior engineers; enforce coding style and lint/timing cleanliness.
• Participate in PPA analysis: synthesize blocks, review area/timing/power reports, and iterate on QoR.
• Collaborate with DV leads to define verification plans and provide directed scenarios for corner cases and power states.
• Support silicon bring-up: DFT/scan guidance and RTL-level debug during lab validation.

Requirements

Key technical requirements and desirable qualifications.

Must-have

• 8+ years of RTL design experience with tape-out ownership on processor or accelerator SoC designs involving dataflow, NoC, memory subsystems, or peripheral integration.
• Deep proficiency in SystemVerilog for synthesis-clean, lint-clean, timing-aware RTL; strong state-machine and datapath design skills.
• Solid understanding of parallel execution models (dataflow, SIMD, systolic arrays) and producer-consumer synchronization.
• Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped registers.
• Experience with low-power RTL techniques (UPF flows, clock gating, power domains, retention registers, AON logic).
• Familiarity with at least one bus protocol (AXI/AHB/APB/TileLink/NoC) at RTL implementation level.
• Proven ability to take RTL through synthesis and timing closure; interpret SDC, STA reports, and synthesis QoR.
• Experience with memory compiler toolchains and producing uArch/spec documents.

Nice-to-have

• Prior ownership of a dataflow engine, NPU, or streaming DSP with explicit token management.
• Experience co-designing with compiler/graph-optimizer teams and familiarity with ONNX/TFLite graph formats.
• Familiarity with NVM controller RTL (MRAM, RRAM), ECC, and program/erase sequencing.
• Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby) and silicon at 12nm or below.
• Exposure to functional safety standards (ISO 26262, IEC 61508) and formal verification for flow-control or protocol compliance.

Education Requirements

Not specified.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.