Lead Product Engineer - Design Verification (MM/VIP)

Role Summary

This role involves driving the development of products and technologies, primarily focusing on Memory domain protocols for verification IP. The Lead Product Engineer (LPE) is responsible for accelerating the adoption of Cadence's VIP Portfolio among top-tier customers, requiring strong verification expertise and technical support for pre-sales activities.

Experience Level

Mid-level, with 4 to 8 years of experience in Design and Verification.

Responsibilities

Key responsibilities include:

• Leading complex projects requiring significant resources and risk management.
• Developing and managing cross-functional programs and initiatives.
• Evaluating technology effectiveness in complex systems.
• Resolving issues and managing vendor relationships regarding product quality.
• Communicating complex ideas and persuading stakeholders.

Requirements

Must-have skills and experience:

• Experience in developing verification environments using System Verilog.
• Working knowledge of UVM methodology.
• Strong problem-solving and debugging skills.
• Familiarity with Memory protocols including SDRAM and DFI protocol.

Education Requirements

Qualifications include a B.Tech/BE/M.Tech/ME or equivalent degree in Electrical, Electronics & Communication, or Computer Science Engineering.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.