Lead Physical Design Engineer

Job Title

Lead Physical Design Engineer

Role Summary

As a Lead Physical Design Engineer you will own physical implementation for complex SoC designs on 5nm and sub-5nm nodes, driving placement & routing flows, timing closure, and physical verification. You will lead a small team, improve methodology and automation, and coordinate with cross-site signoff teams to deliver production-quality silicon.

Experience Level

Senior level - requires 15+ years of hands-on experience in physical design and backend digital flows.

Responsibilities

Primary responsibilities include end-to-end physical implementation, team leadership, and automation and methodology improvements:

• Lead top-down and bottom-up physical design integration for complex SoC architectures at 5nm and below.
• Develop and execute full backend flow for blocks and full-chip: floorplanning, partitioning, placement, CTS, routing, extraction, and GDSII stream-out.
• Manage timing closure and functional ECOs; collaborate with signoff teams for final closure.
• Own signoff physical verification activities (DRC/LVS) and ensure design quality.
• Build, scale and optimize automation flows and production-grade scripts to improve reuse and turnaround time.
• Mentor and lead a small physical design team across sites and time zones; set execution goals and resolve technical bottlenecks.
• Drive measurable improvements in turnaround time, layout quality, and engineering benchmarks.

Requirements

Required and preferred skills, tools and experience.

• Must-have: 15+ years hands-on experience in physical design from RTL synthesis to final GDSII.
• Must-have: Deep proficiency in timing constraints, timing closure and physical constraints.
• Must-have: Hands-on experience with EDA physical implementation and signoff tools (Cadence, Synopsys, Siemens toolsets such as Genus, Innovus, Quantus, Tempus, DC, Star-RCXT, PT, PrimeRail, Voltus, Redhawk).
• Must-have: Strong scripting and automation skills, especially Tcl and Perl, for production-grade flows.
• Must-have: Proven track record debugging complex physical and timing issues and collaborating across teams and time zones.
• Nice-to-have: Prior experience driving methodology improvements and building automation from scratch for SoC flows.

Education Requirements

Not specified.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.