Lead Physical Design Engineer

Job Title

Lead Physical Design Engineer

Role Summary

Lead physical implementation and signoff for top-level and block-level ASIC designs on 28nm nodes and below. The role is based in the MIC team in Bangalore and owns the full physical-design flow from floorplanning through GDS.

Primary mission: deliver tape-out–ready layouts with timing, power and physical verification signoff while guiding and coordinating implementation flows across the team.

Experience Level

Senior — minimum 10 years total industry experience, with at least 8 years focused on chip- or block-level physical design.

Responsibilities

Accountable for end-to-end physical design and signoff activities; provide technical leadership and direction to the implementation team.

• Own physical implementation from floorplan to GDS: synthesis, placement, CTS, routing, extraction, and tape-out.
• Plan and execute top-level and block-level P&R and timing closure (block/full-chip/SOC/mixed-signal paths).
• Develop and maintain timing constraints (SDC) and perform hierarchical and flat timing analysis and bring-up.
• Perform static timing analysis (STA), Logical Equivalence Checking (LEC) debugging, and timing signoff.
• Implement low-power methodologies and flows (CPF/UPF, CLP) and support power-reduction techniques.
• Estimate power, design/analyze power grids, and perform static and dynamic IR drop analysis.
• Perform physical verification analysis: DRC, LVS, ERC and PERC rule file review and fixes.
• Integrate IP and manage interface paths, signal integrity and crosstalk mitigation.
• Provide clear direction to engineers on implementation and signoff flows; participate in all design stages.

Requirements

Key technical skills and experience required for successful execution of the role.

• Must-have: At least 10 years of semiconductor experience with a minimum of 8 years in physical design at chip or block level.
• Must-have: Proven experience with P&R flows, CTS, timing closure, extraction, physical verification and tape-out on 28nm or below.
• Must-have: Strong knowledge of EDA tool flows and Cadence foundation flows; RTL-to-GDS experience desired.
• Must-have: Experience in timing constraint development, hierarchical and flat timing analysis, and STA signoff methodologies.
• Must-have: Familiarity with low-power flows (CPF/UPF) and power integrity analysis (IR drop, power grid design).
• Nice-to-have: Experience with Tcl/Tk and Perl scripting.

Education Requirements

Bachelor's degree in Electrical Engineering, Electronics & Communication Engineering, or a related electronics discipline from a recognized institute.

About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.