Lead Physical Design Engineer

Job Title

Lead Physical Design Engineer

Role Summary

Lead and execute physical design and implementation for AI NPU and complex SoC/ASIC projects. Own stages from RTL synthesis through floorplanning, placement, clock tree synthesis, routing, and timing closure to deliver tapeout-quality designs.

Provide technical leadership to define physical design strategy per technology node, improve design flows and automation, and coordinate with verification, power, DFT, and system teams to meet performance, power and area goals.

Experience Level

Senior — minimum 8 years' experience in digital physical design of complex SoCs or ASICs.

Responsibilities

Primary responsibilities center on physical implementation, cross-team collaboration, and process/methodology improvements.

• Execute physical design flow: floorplanning, power planning, placement, CTS, routing, and timing closure.
• Perform static timing analysis and converge timing to meet signoff requirements.
• Collaborate with physical verification teams to resolve DRC/LVS/antenna issues.
• Work with power integrity teams to address IR drop and EM concerns and optimize power.
• Coordinate with RTL design, verification, and DFT teams to ensure integration and project milestones.
• Analyze and resolve issues related to timing, area, and power trade-offs.
• Develop and maintain scripts and automation to improve physical design efficiency.
• Contribute to continuous improvement of methodologies and generate implementation reports and documentation.
• Define physical design strategy for target technology nodes and mentor junior engineers.

Requirements

Must-have skills and experience:

• Minimum 8 years' experience in digital physical design for complex SoCs or ASICs.
• Proficiency with industry-standard EDA tools (examples: Cadence Innovus/Genus/Tempus or Synopsys Fusion Compiler/PrimeTime) and physical verification tools (e.g., Mentor Calibre).
• Strong understanding of floorplanning, placement, routing, clock tree synthesis, and physical verification issues.
• Solid experience in static timing analysis and timing-closure techniques.
• Experience with scripting for automation (Tcl, Perl, Python).
• Familiarity with deep sub-micron process technologies and VLSI design principles.
• Excellent problem-solving, collaboration, and communication skills.

Nice-to-have:

• Experience leading teams or mentoring engineers in physical design projects.
• Prior work on AI NPU or high-performance compute SoCs.
• Hands-on experience with power integrity analysis and PPA optimization.
• Experience improving/defining physical design methodology and flows.

Education Requirements

Bachelor's or Master's degree in VLSI, Electronics Engineering, or a related field (as stated in the posting).

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.