Job Title
Lead Performance Modeling Architect, CPU Fabric and LLC
Role Summary
Technical lead responsible for driving performance modeling of cache hierarchies and coherent I/O interconnects across automotive and data center platforms. The role combines hands-on modeling, cross-functional liaison with Architecture/RTL/Software teams, and people leadership for a team of performance-modeling engineers.
Experience Level
Senior β requires substantial industry experience. The posting specifies 8+ years in high-performance silicon architecture and experience managing technical teams or complex projects.
Responsibilities
Primary responsibilities include defining modeling strategy, leading the modeling team, and resolving cross-team performance trade-offs.
- Define long-term vision and approach for modeling infrastructure (cycle-accurate, analytical, stochastic, hybrid).
- Lead and mentor a team of modeling engineers; conduct code and architecture reviews.
- Serve as primary liaison between Architecture, RTL build, and Software to diagnose and resolve performance bottlenecks.
- Drive adoption of advanced methodologies (emulation/simulation hybrids, AI-based optimization) to accelerate delivery.
- Plan and prioritize simulation workloads and engineering effort across multiple concurrent projects in automotive and data center domains.
Requirements
Must-have technical skills and experience; items marked as Nice-to-have where applicable.
-
Must-have: 8+ years in high-performance silicon architecture or performance modeling; demonstrated experience managing technical teams or complex projects.
-
Must-have: Deep knowledge of cache-coherency protocols (e.g., AMBA CHI, MESI), memory sub-systems, and high-speed interconnect fabric design.
-
Must-have: Significant experience architecting and implementing large-scale simulators in C++ or SystemC, focused on modularity and speed.
-
Must-have: Competence using statistical analysis to validate model accuracy against RTL or silicon and to explain performance cliffs to stakeholders.
-
Nice-to-have: Full-stack experience from high-level modeling to RTL integration and post-silicon tuning.
-
Nice-to-have: Participation or influence in industry standards bodies (e.g., CXL Consortium) or a record of published architectural research.
-
Nice-to-have: Proven scalability work across both low-latency safety-critical systems and large high-bandwidth cloud-scale networks.
Education Requirements
Master's or Ph.D. in Computer Engineering or a related field, or equivalent practical experience.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

Date Posted: 2026-05-07