Lead PERC Rule Deck Development Engineer

Job Title

Lead PERC Rule Deck Development Engineer

Role Summary

Own and drive development, validation, and deployment of Calibre PERC rule decks and methodology for ESD, latch-up, power-domain, connectivity, and reliability verification across IP, block, subsystem, and SoC levels.

Work as a technical lead with design, CAD, technology, foundry, and product teams to translate signoff requirements into scalable PERC checks, enable flows, and provide debug and release readiness.

Experience Level

Senior — requires significant hands-on experience; posting specifies at least 10 years of relevant industry experience.

Responsibilities

Primary responsibilities for this role include development, enablement, and support of PERC rule decks and related verification flows.

• Lead development, enhancement, validation, and release of Calibre PERC rule decks for ESD, latch-up, power-domain, connectivity, and reliability checks.
• Translate technology, product, and signoff requirements into scalable, maintainable PERC checks and verification methodologies.
• Enable PERC flows across IP, block, subsystem, and SoC stages and integrate with LVS, extraction, and physical verification signoff flows.
• Debug complex PERC/LVS issues with design, layout, CAD, and technology teams; provide root-cause analysis and closure recommendations.
• Develop automation scripts, regression suites, quality checks, and reporting utilities to improve efficiency and traceability.
• Partner with analog, AMS, CAD, product, and technology stakeholders to define verification requirements and deployment plans.
• Establish best practices for rule coding, validation, test-case creation, documentation, version control, and release readiness.
• Support design milestones such as IP readiness, MPW/FDIP development, tapeout preparation, and customer signoff readiness.
• Monitor rule deck quality, resolve priority issues, and report status to stakeholders and management.
• Mentor junior engineers and build team competency in PERC, ESD, and physical verification.

Requirements

Core technical skills and experience required; preferred items listed separately.

Must-have

• Hands-on expertise in PERC rule development, debugging, validation, and deployment in production design environments (Calibre PERC/LVS).
• Deep understanding of ESD fundamentals (HBM, CDM, system-level models) and ESD protection verification methodologies.
• Proficiency in scripting/programming for automation and flow development (TCL, Perl, Python, SKILL, TVF/SVRF).
• Good understanding of analog and mixed-signal design flows including schematic, layout, extraction, and signoff dependencies.
• Solid knowledge of CMOS fundamentals and advanced-node / FinFET device/layout/reliability effects.
• Experience leading physical verification flows across IP to SoC levels and working with cross-functional teams across time zones.
• Strong communication, ownership, and mentorship skills to act as a technical lead.

Nice-to-have

• Experience with Cadence Virtuoso, Cadence Quantus or equivalent extraction/verification platforms.
• Exposure to AMS verification, transistor-level RC extraction, post-layout verification, or RC-aware debug.
• Experience defining methodology roadmaps, reusable verification platforms, or productivity automation for large organizations.

Education Requirements

BTech/BE/ME/MTech in Electronics & Communication, Electrical Engineering, Microelectronics, VLSI, or a related discipline; the posting specifies at least 10 years of relevant industry experience.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.