Lead PDN EMIR Engineer

Job Title

Lead PDN EMIR Engineer

Role Summary

Lead the power distribution network (PDN) and EM/IR signoff activities for complex SoCs. Own PDN signoff criteria, power-integrity closure across operating modes, and chip-package co-optimization.

Work with Physical Design, Package, Thermal, DFT and EDA vendors to deliver signoff-ready silicon, improve PDN signoff methodology, and mentor engineers across projects.

Experience Level

Senior - requires 8+ years of experience in Physical Design, Power Integrity, or signoff for semiconductor SoCs.

Responsibilities

Primary responsibilities include technical leadership of PDN signoff, methodology development, and cross-functional coordination.

• Own full-chip and subsystem PDN signoff and define signoff criteria across project milestones.
• Drive power-integrity closure for functional, DFT, LBIST, capture, and stress modes.
• Lead package-aware IR/EM analysis and chip-package co-optimization, including bump planning and RLC considerations.
• Define and review power-grid architecture, power-switch strategy, decoupling methodology, and bump/power distribution planning.
• Perform Vmin, peak-EM, dynamic-IR, and thermal-aware analyses and drive hotspot closure with minimal PPA impact.
• Develop and automate PDN signoff flows; improve runtime, capacity, dashboarding, and regression infrastructure.
• Collaborate with EDA vendors for tool debugging and feature enhancement.
• Support silicon bring-up, measurement correlation, and post-silicon debug.
• Provide technical risk assessments, present signoff status to stakeholders, and ensure on-time delivery for tapeout milestones.
• Lead design reviews for high-risk blocks and top-level integrations.

Requirements

Must-have technical skills and experience for successful performance in this role.

• 8+ years experience in Physical Design, Power Integrity, or PDN signoff for complex SoCs.
• Proven track record of full-chip PDN signoff and defining signoff criteria across project stages.
• Experience with package-aware IR/EM analysis and chip-package co-optimization workflows.
• Strong automation skills (TCL, Python, Shell) to build and maintain PDN flows and regression frameworks.
• Practical experience with industry EDA tools and vendor collaboration (Ansys/Cadence/Synopsys or equivalent).
• Ability to analyze Vmin, peak EM, dynamic IR, and perform thermal-aware correlation.
• Leadership experience: mentoring engineers, running technical reviews, and defining signoff governance.
• Excellent communication and cross-functional collaboration skills with PD, Package, Thermal, and DFT teams.
• Nice-to-have: experience improving signoff runtime/capacity infrastructure, advanced decap planning, and large-scale regression systems.

Education Requirements

B.Tech or M.Tech in Electronics, Electrical Engineering, VLSI, or a related technical field.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.