Lead, MTS Verification Engineering

Job Title

Lead, MTS Verification Engineering

Role Summary

Lead a verification team responsible for planning, implementing, and delivering verification solutions for MTS (memory/test/system) IP and subsystems. Work with design, architecture, validation, and software teams to define verification strategy, drive test development, and ensure product quality.

Expect hands-on technical leadership: authoring verification environments, directing block- and system-level verification, and mentoring engineers to meet schedule and quality targets.

Experience Level

Senior — Lead-level role. Typical experience: 8+ years in semiconductor design verification or equivalent industry experience.

Responsibilities

Accountabilities and typical activities for the role:

• Define verification strategy and plans for IP, block, and SoC-level deliverables; track progress and report risks.
• Lead development of SystemVerilog/UVM testbenches, verification components, and reusable IP verification infrastructure.
• Implement and maintain automated regression, CI, and continuous verification flows; integrate with emulation and FPGA prototyping as needed.
• Drive functional coverage closure, assertion-based verification, and debug root-cause analysis for functional failures.
• Coordinate cross-team integration and verification efforts with design, firmware, validation, and architecture groups.
• Mentor and grow verification engineers; perform design/verification reviews and provide technical guidance.
• Establish and enforce verification best practices, tooling, and metrics to improve productivity and quality.

Requirements

Required skills and experience (must-have vs nice-to-have):

• Must-have: Proven leadership of verification teams and delivery of complex semiconductor IP or subsystems; hands-on experience building SystemVerilog/UVM environments and running large regressions.
• Must-have: Strong debug skills using simulators, waveform analysis, assertions, and functional coverage closure techniques.
• Must-have: Experience with verification tools and flows: simulators, emulators, FPGA prototyping, coverage tools, and CI systems.
• Must-have: Proficiency in scripting (Python, Perl, or Tcl) for testbench automation and infrastructure development.
• Nice-to-have: Experience with SoC-level verification, UVM factory/multi-language integration, formal verification, or low-power verification techniques.
• Nice-to-have: Domain experience with memory interfaces (DDR), high-speed SerDes, PHYs, or security-IP verification.
• Strong communication, cross-team collaboration, and project management skills to drive verification schedules and resolve technical risks.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is expected; a Master's or PhD is preferred. Equivalent practical industry experience may be accepted in lieu of a degree.

About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.