Lead IP Block level Verification Engineer

Job Title

Lead IP Block level Verification Engineer

Role Summary

Lead verification of Network-on-Chip (NoC) IP blocks and related subsystems at block and subsystem level. Architect, develop and execute simulation- and formal-based verification environments to prove functional correctness for IPs and SOC blocks.

Experience Level

Senior-level — 8+ years of verification or silicon/ASIC experience; experience leading verification efforts and collaborating across sites/time zones.

Responsibilities

Primary responsibilities include planning and executing verification activities, architecting test environments, and driving coverage closure.

• Lead and plan verification for complex digital design blocks by understanding architecture and specifications.
• Collaborate with architects and design engineers to produce comprehensive verification test plans.
• Design and architect testbenches in SystemVerilog and UVM for efficient verification.
• Develop constrained-random and directed verification environments; implement assertions (SVA) and use formal tools where applicable.
• Debug failures with design engineers to deliver functionally correct blocks.
• Define and track coverage metrics; perform coverage analysis and close verification gaps.
• Drive regression management and verification infrastructure at block or subsystem scale.

Requirements

Summary of required and preferred skills for the role.

• Must-have: Proven experience leading block-level verification of complex digital designs; strong SystemVerilog and UVM testbench development skills.
• Must-have: Experience with constrained-random verification, assertions (SVA), coverage-driven verification, and debugging at block/subsystem level.
• Must-have: Familiarity with ASIC/SoC development flow and regression/verification management practices.
• Preferred: Experience with simulation tools such as Synopsys VCS or Cadence IES and with verification methodologies like OVM/VMM.
• Preferred: Experience with NoC verification and protocol verification (AXI3/4, DDR4/5, HBM, PCIe, processors, graphics).
• Preferred: Background as a verification architect, gate-level simulation, power/reset verification, contention checking, abstraction techniques, or verification database/regression tooling.
• Preferred: Experience with formal property checking tools (Cadence IEV, Jasper, Synopsys VC-Formal/Magellan) is a plus.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. The posting specifies 8+ years of related experience.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.