Lead Engineer – IC Design (STA Lead)

Job Title

Lead Engineer – IC Design (STA Lead)

Role Summary

Lead engineer responsible for static timing analysis (STA) and backend (BE) implementation for high-performance SoCs and ASICs. The role leads STA execution, constraints development, timing sign-off and PPA optimization across operating modes and process corners.

Works cross-functionally with RTL, DFT, PnR and verification teams to drive timing closure, automation, and methodology improvements while mentoring junior engineers.

Experience Level

Senior — requires 7+ years of experience in ASIC physical design and backend implementation.

Responsibilities

Key responsibilities include:

• Develop, manage and validate timing constraints for RTL-to-GDSII flows in collaboration with design and DFT teams.
• Execute STA for digital blocks and top-level designs and own timing sign-off across modes and corners.
• Generate CTS specifications with PnR teams and implement timing ECOs to resolve critical paths.
• Run logical equivalence and timing report analysis using industry-standard tools.
• Implement and verify low-power methodologies and UPF/CPF checks.
• Perform CDC, false-path and multi-cycle path checks and ensure correct timing constraints.
• Lead end-to-end physical design flow for complex SoCs and IP blocks (RTL handoff to GDSII) and optimize PPA.
• Manage synthesis strategies, sign-off criteria (timing, IR drop, EM, DRC/LVS) and integration with verification and packaging teams.
• Drive EDA tool flow automation and methodology enhancements to improve scalability and efficiency.
• Mentor and guide junior engineers; lead a small engineering team.

Requirements

Must-have:

• 7+ years of ASIC physical design experience focused on backend implementation and STA.
• Hands-on experience with industry EDA tools such as Cadence (Genus, Innovus, Tempus, LEC, CLP) or Synopsys (ICC2, Fusion Compiler, PrimeTime).
• Strong skills in synthesis, constraints creation, timing analysis and timing-fix methodologies.
• Solid understanding of architecture-to-GDSII flows and sign-off requirements.
• Experience with PPA optimization and low-power implementation methodologies.
• Excellent problem-solving and communication skills.

Nice-to-have:

• Chip-level integration, hierarchical design methodologies, DFT, floorplanning, PnR and physical verification/IR analysis experience.
• Exposure to multi-clock, multi-voltage and multi-domain designs.
• Experience leading small teams (4–10 members).
• Automation expertise with Perl, Tcl/Tk, or Python.
• Experience collaborating across multiple sites.

Education Requirements

Bachelor’s or Master’s degree in Electrical and Computer Engineering (ECE), Electrical Engineering (EEE), VLSI or a related field.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.