Lead Engineer – IC Design (STA Lead)

Job Title

Lead Engineer – IC Design (STA Lead)

Role Summary

Lead and perform back-end (BE) implementation tasks for high-performance SoCs and ASICs with emphasis on constraints management, synthesis, and Static Timing Analysis (STA). The role owns timing sign-off, PPA optimization, and cross-team coordination across RTL, DFT, PnR and verification.

Based in Hyderabad, this is a hands-on technical lead position responsible for improving timing methodology, automating EDA flows, and mentoring junior engineers.

Experience Level

Senior — typically requires 7+ years of ASIC physical design experience and experience leading small engineering teams.

Responsibilities

Accountable for timing closure and end-to-end BE implementation for complex blocks and SoCs. Key responsibilities include:

• Develop, manage and validate timing constraints for RTL-to-GDSII flows in collaboration with design and DFT teams.
• Execute STA for digital blocks and top-level designs and interpret timing reports.
• Create CTS specifications with PnR engineers and implement timing ECOs to resolve critical paths.
• Perform checks for CDC, false paths, and multicycle paths; run logical equivalence checks.
• Own and optimize power, performance, and area (PPA) targets, including low-power implementation checks.
• Drive EDA tool flow automation and methodology improvements for scalability and efficiency.
• Manage synthesis strategies, sign-off criteria (timing, IR drop, EM, DRC/LVS), and collaborate across RTL, DFT, verification, and packaging teams.
• Lead and mentor engineers, and coordinate multi-site collaboration where applicable.

Requirements

Must-have technical skills and experience; preferred items noted.

• 7+ years of experience in ASIC physical design, with strong hands-on STA and sign-off experience.
• Hands-on expertise with industry-standard EDA tools such as Cadence (Genus, Innovus, Tempus, LEC, CLP) or Synopsys (ICC2, Fusion Compiler, PrimeTime).
• Strong background in synthesis, constraints, timing margins, and timing analysis/fixing.
• Solid understanding of architecture-to-GDSII flows and sign-off requirements (timing, IR drop, EM, DRC/LVS).
• Excellent problem-solving and communication skills; ability to lead cross-functional work.
• (Nice-to-have) Experience with chip-level integration, hierarchical design methodologies, and multi-clock/multi-voltage domains.
• (Nice-to-have) Knowledge of low-power techniques (UPF/CPF, power gating, DVFS), DFT, floorplanning, PnR, IR analysis, and automation using Perl/TCL/Python.

Education Requirements

Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), VLSI or a related technical field.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.